Analysis & Synthesis report for RAM4GS
Thu Jul 23 02:20:40 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis IP Cores Summary
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Port Connectivity Checks: "UFM:UFM_inst"
 13. Analysis & Synthesis Messages
 14. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Jul 23 02:20:40 2020           ;
; Quartus II 32-bit Version   ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name               ; RAM4GS                                          ;
; Top-level Entity Name       ; RAM4GS                                          ;
; Family                      ; MAX II                                          ;
; Total logic elements        ; 178                                             ;
; Total pins                  ; 62                                              ;
; Total virtual pins          ; 0                                               ;
; UFM blocks                  ; 1 / 1 ( 100 % )                                 ;
+-----------------------------+-------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EPM240T100C5       ;                    ;
; Top-level entity name                                                      ; RAM4GS             ; RAM4GS             ;
; Family name                                                                ; MAX II             ; Cyclone IV GX      ;
; Safe State Machine                                                         ; On                 ; Off                ;
; Power-Up Don't Care                                                        ; Off                ; On                 ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 1           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                      ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                        ; File Name with Absolute Path                              ; Library ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+
; RAM4GS.v                         ; yes             ; User Verilog HDL File            ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v   ;         ;
; RAM4GS.mif                       ; yes             ; User Memory Initialization File  ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.mif ;         ;
; UFM.v                            ; yes             ; User Wizard-Generated File       ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v      ;         ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------+---------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 178   ;
;     -- Combinational with no register       ; 82    ;
;     -- Register only                        ; 29    ;
;     -- Combinational with a register        ; 67    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 57    ;
;     -- 3 input functions                    ; 41    ;
;     -- 2 input functions                    ; 42    ;
;     -- 1 input functions                    ; 8     ;
;     -- 0 input functions                    ; 1     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 162   ;
;     -- arithmetic mode                      ; 16    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 9     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 96    ;
; Total logic cells in carry chains           ; 17    ;
; I/O pins                                    ; 62    ;
; UFM blocks                                  ; 1     ;
; Maximum fan-out node                        ; RCLK  ;
; Maximum fan-out                             ; 54    ;
; Total fan-out                               ; 643   ;
; Average fan-out                             ; 2.67  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                    ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                    ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; |RAM4GS                                                   ; 178 (178)   ; 96           ; 1          ; 62   ; 0            ; 82 (82)      ; 29 (29)           ; 67 (67)          ; 17 (17)         ; 0 (0)      ; |RAM4GS                                                                ; work         ;
;    |UFM:UFM_inst|                                         ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst                                                   ; work         ;
;       |UFM_altufm_none_1br:UFM_altufm_none_1br_component| ; 0 (0)       ; 0            ; 1          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component ; work         ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                       ;
+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance      ; IP Include File                                      ;
+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+
; Altera ; ALTUFM_NONE  ; 13.0    ; N/A          ; N/A          ; |RAM4GS|UFM:UFM_inst ; //vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v ;
+--------+--------------+---------+--------------+--------------+----------------------+------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 96    ;
; Number of registers using Synchronous Clear  ; 6     ;
; Number of registers using Synchronous Load   ; 3     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 10    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; nRCS~reg0                              ; 1       ;
; nRWE~reg0                              ; 1       ;
; nRRAS~reg0                             ; 1       ;
; nRCAS~reg0                             ; 1       ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM4GS|S[0]               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |RAM4GS|C1Submitted        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst"                                                                          ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                             ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; ardin   ; Input  ; Info     ; Stuck at GND                                                                        ;
; busy    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; osc     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rtpbusy ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Jul 23 02:20:35 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file ram4gs.v
    Info (12023): Found entity 1: RAM4GS
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
    Info (12023): Found entity 1: UFM_altufm_none_1br
    Info (12023): Found entity 2: UFM
Info (12127): Elaborating entity "RAM4GS" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
Info (12128): Elaborating entity "UFM_altufm_none_1br" for hierarchy "UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component"
Warning (18029): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated
Warning (18029): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated
Warning (18029): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated
Warning (18029): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated
Warning (18029): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated
Warning (18029): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated
Warning (18029): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated
Warning (18029): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated
Info (21057): Implemented 241 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 25 input pins
    Info (21059): Implemented 29 output pins
    Info (21060): Implemented 8 bidirectional pins
    Info (21061): Implemented 178 logic cells
    Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Peak virtual memory: 303 megabytes
    Info: Processing ended: Thu Jul 23 02:20:41 2020
    Info: Elapsed time: 00:00:06
    Info: Total CPU time (on all processors): 00:00:05


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg.


