diff --git a/pogo_rig/firmware/exixe.ioc b/pogo_rig/firmware/exixe.ioc deleted file mode 100644 index 19e9920..0000000 --- a/pogo_rig/firmware/exixe.ioc +++ /dev/null @@ -1,56 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -File.Version=6 -KeepUserPlacement=false -Mcu.Family=STM32F0 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=SPI1 -Mcu.IP3=SYS -Mcu.IPNb=4 -Mcu.Name=STM32F030F4Px -Mcu.Package=TSSOP20 -Mcu.Pin0=PA4 -Mcu.Pin1=PA5 -Mcu.Pin2=PA6 -Mcu.Pin3=PA7 -Mcu.Pin4=VP_SYS_VS_Systick -Mcu.PinsNb=5 -Mcu.UserConstants= -Mcu.UserName=STM32F030F4Px -MxCube.Version=4.22.1 -MxDb.Version=DB.4.0.221 -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false -PA4.GPIOParameters=GPIO_Label -PA4.GPIO_Label=SPI1_CS -PA4.Locked=true -PA4.Signal=GPIO_Output -PA5.Mode=Full_Duplex_Master -PA5.Signal=SPI1_SCK -PA6.Mode=Full_Duplex_Master -PA6.Signal=SPI1_MISO -PA7.Mode=Full_Duplex_Master -PA7.Signal=SPI1_MOSI -PCC.Checker=false -PCC.Line=STM32F0x0 Value Line -PCC.MCU=STM32F030F4Px -PCC.PartNumber=STM32F030F4Px -PCC.Seq0=0 -PCC.Series=STM32F0 -PCC.Temperature=25 -PCC.Vdd=3.6 -PinOutPanel.RotationAngle=0 -RCC.FamilyName=M -RCC.IPParameters=FamilyName,PLLCLKFreq_Value,TimSysFreq_Value -RCC.PLLCLKFreq_Value=8000000 -RCC.TimSysFreq_Value=8000000 -SPI1.CalculateBaudRate=4.0 MBits/s -SPI1.Direction=SPI_DIRECTION_2LINES -SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate -SPI1.Mode=SPI_MODE_MASTER -SPI1.VirtualType=VM_MASTER -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick diff --git a/pogo_rig/firmware/pogixe.ioc b/pogo_rig/firmware/pogixe.ioc index 3211f09..c126f23 100644 --- a/pogo_rig/firmware/pogixe.ioc +++ b/pogo_rig/firmware/pogixe.ioc @@ -10,16 +10,19 @@ Mcu.IP4=USART1 Mcu.IPNb=5 Mcu.Name=STM32F030F4Px Mcu.Package=TSSOP20 -Mcu.Pin0=PA2 -Mcu.Pin1=PA3 -Mcu.Pin2=PA4 -Mcu.Pin3=PA5 -Mcu.Pin4=PA6 -Mcu.Pin5=PA7 -Mcu.Pin6=PA13 -Mcu.Pin7=PA14 -Mcu.Pin8=VP_SYS_VS_Systick -Mcu.PinsNb=9 +Mcu.Pin0=PA0 +Mcu.Pin1=PA1 +Mcu.Pin10=PA14 +Mcu.Pin11=VP_SYS_VS_Systick +Mcu.Pin2=PA2 +Mcu.Pin3=PA3 +Mcu.Pin4=PA4 +Mcu.Pin5=PA5 +Mcu.Pin6=PA6 +Mcu.Pin7=PA7 +Mcu.Pin8=PB1 +Mcu.Pin9=PA13 +Mcu.PinsNb=12 Mcu.UserConstants= Mcu.UserName=STM32F030F4Px MxCube.Version=4.23.0 @@ -29,6 +32,14 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false +PA0.GPIOParameters=GPIO_Label +PA0.GPIO_Label=LED1 +PA0.Locked=true +PA0.Signal=GPIO_Output +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=EXIXE_RST +PA1.Locked=true +PA1.Signal=GPIO_Output PA13.Mode=Serial_Wire PA13.Signal=SYS_SWDIO PA14.Mode=Serial_Wire @@ -47,6 +58,10 @@ PA6.Mode=Full_Duplex_Master PA6.Signal=SPI1_MISO PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI +PB1.GPIOParameters=GPIO_Label +PB1.GPIO_Label=USER_BUTTON +PB1.Locked=true +PB1.Signal=GPIO_Input PCC.Checker=false PCC.Line=STM32F0x0 Value Line PCC.MCU=STM32F030F4Px diff --git a/pogo_rig/pcb/clock.lbr b/pogo_rig/pcb/clock.lbr index 4861fd4..70be9a9 100644 --- a/pogo_rig/pcb/clock.lbr +++ b/pogo_rig/pcb/clock.lbr @@ -1,12 +1,12 @@ - + - + @@ -259,8 +259,7 @@ by exp-lbrs.ulp - - + @@ -4896,61 +4895,61 @@ package type ST <b>PIN HEADER</b> - - - - - - - - + + + + - - - - - - - - + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - -G -HV -G -5V -EN + + + + + + + + + + +G +HV +G +5V +EN <b>PIN HEADER</b> diff --git a/pogo_rig/pcb/exixe_pogo.brd b/pogo_rig/pcb/exixe_pogo.brd index 4f8fa75..c82a19c 100644 --- a/pogo_rig/pcb/exixe_pogo.brd +++ b/pogo_rig/pcb/exixe_pogo.brd @@ -1,25 +1,39 @@ - + - + - + + + + + + + + + + + + + + + - - - + + + - - + + @@ -34,8 +48,8 @@ - - + + @@ -44,8 +58,8 @@ - - + + @@ -160,6 +174,16 @@ + + + + + + + + + + @@ -284,13 +308,13 @@ 9 0 ANODE -DL -PB3 +DL +PB3 PF0 -PF1 -PB6 +PF1 +PB6 -DR +DR @@ -472,68 +496,67 @@ by exp-lbrs.ulp <b>PIN HEADER</b> - - - - - - - - + + + + - - - - - - - - + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - -G -HV -G -5V -EN + + + + + + + + + + +G +HV +G +5V +EN - - + @@ -718,40 +741,39 @@ MAX3223-MAX3243.pdf - -<b>EAGLE Design Rules</b> + +<b>SparkFun 2 Layer Design Rule Checks - STANDARD/TIGHT/FAB-LIMIT</b> <p> -Die Standard-Design-Rules sind so gewählt, dass sie für -die meisten Anwendungen passen. Sollte ihre Platine -besondere Anforderungen haben, treffen Sie die erforderlichen -Einstellungen hier und speichern die Design Rules unter -einem neuen Namen ab. -<b>EAGLE Design Rules</b> +These rules have been curated by SparkFuns DFM commitee. After doing much research, communicating with our multiple fab houses, and getting quotes of various designs, we have compiled three DRU files. <p> -The default Design Rules have been set to cover -a wide range of applications. Your particular design -may have different requirements, so please make the -necessary adjustments and save your customized -design rules under a new name. +<b>STANDARD:</b> This is more of a "best case scenario" set of limitations. If your design has the space, and/or you have the time to work within these parameters, please do. Larger trace width and clearance makes for easier visual inspection of the PCB while troubleshooting (useful in production and to the end user). It also allows for better ability to hack a trace (if you are crazy enough to scrape away the mask and solder to a trace). Another thing to keep in mind is that more metal is just more robust. +<p> +<b>TIGHT:</b> This is where cost comes into play. We have found that most fab houses begin to add extra charges when you go smaller than these specs. In some cases, going to less than 15 mil trace can increase the cost by 10%. (This is why we have set the min drill on this DRU to 15 mil) Same story for traces thinner than 7 mil. To avoid those extra charges, then stay within the rules of this DRU. +<p> +<b>FAB-LIMIT:</b> These set of rules are at the very limit of most fab houses capabilities. You will pay more for these specs, and it should be used on designs that have a darned good reason to need 4 mil vias and 4 mil traces. +<p> +**NOTE Clearance, Distance, Sizes, and Restring are all set to different limits in each of these three DRU files. Please compare the files within the CAM job editor window of eagle to see all the numbers. +<p> +***NOTE, Please set your Net Classes to default (0mil for all settings), so that it won't effect the DRC when you run it with these settings. - - - - - - - - - - + + + + + + + + + + - - + + - - + + @@ -761,15 +783,15 @@ design rules under a new name. - + - + - + - + - + @@ -786,7 +808,7 @@ design rules under a new name. - + @@ -794,7 +816,7 @@ design rules under a new name. - + @@ -907,24 +929,24 @@ design rules under a new name. - - - - - - - - - - - - + + + + + + + + + + + + - - + + - - + + @@ -933,7 +955,7 @@ design rules under a new name. - + @@ -941,6 +963,12 @@ design rules under a new name. + + + + + + @@ -954,7 +982,7 @@ design rules under a new name. - + @@ -966,10 +994,22 @@ design rules under a new name. - + + + + + + + + + + + + + @@ -979,12 +1019,30 @@ design rules under a new name. + + + + + + + + + + + + + + + + + + - + @@ -996,7 +1054,6 @@ design rules under a new name. - @@ -1007,159 +1064,493 @@ design rules under a new name. - - - - - - - - + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + + - - + + + + + + + + - - + + + + + + + + + + + + + - - + + + + + + + + + + + + - - + + + + + + + + - - + + + + + + + + + + + + - - + + + + + + + + + + + - - + + + + + + + + + + - - + + + + + + + + + + - - + + + + + + + + + + + + + - - + + + + + + + + + + + + + + - - + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + + + - - + + + + + + + + + + + + + + + - - + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pogo_rig/pcb/exixe_pogo.pdf b/pogo_rig/pcb/exixe_pogo.pdf new file mode 100644 index 0000000..e836ccc Binary files /dev/null and b/pogo_rig/pcb/exixe_pogo.pdf differ diff --git a/pogo_rig/pcb/exixe_pogo.sch b/pogo_rig/pcb/exixe_pogo.sch index 6dd05c1..8cc4e31 100644 --- a/pogo_rig/pcb/exixe_pogo.sch +++ b/pogo_rig/pcb/exixe_pogo.sch @@ -1,6 +1,6 @@ - + @@ -274,13 +274,13 @@ 9 0 ANODE -DL -PB3 +DL +PB3 PF0 -PF1 -PB6 +PF1 +PB6 -DR +DR @@ -984,68 +984,67 @@ by exp-lbrs.ulp <b>PIN HEADER</b> - - - - - - - - + + + + - - - - - - - - + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - -G -HV -G -5V -EN + + + + + + + + + + +G +HV +G +5V +EN - - + <b>CAPACITOR</b><p> @@ -6038,9 +6037,7 @@ MAX3223-MAX3243.pdf - - @@ -6061,14 +6058,27 @@ MAX3223-MAX3243.pdf - - + + + + + + + + + + + + + + + @@ -6080,16 +6090,16 @@ HV pullup resistor - + - - + + - + @@ -6100,16 +6110,14 @@ HV pullup resistor - - - - + + - + - + @@ -6117,20 +6125,33 @@ HV pullup resistor - + - - - + + + + + + + + + + + + + + + + @@ -6149,6 +6170,18 @@ HV pullup resistor + + + + + + + + + + + + @@ -6191,11 +6224,6 @@ HV pullup resistor - - - - - @@ -6206,7 +6234,33 @@ HV pullup resistor - + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -6240,12 +6294,6 @@ HV pullup resistor - - - - - - @@ -6253,11 +6301,6 @@ HV pullup resistor - - - - - @@ -6269,208 +6312,218 @@ HV pullup resistor - + - - + - - - - + + + + - + - - + + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - + - - - - + + + + - - + + - - + + - - + + - - + + - + - - - + + + - - + + - + - + - + @@ -6542,6 +6595,105 @@ HV pullup resistor + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +