From 1e012699af2c2334163d5606e8083238214f7f2b Mon Sep 17 00:00:00 2001
From: David Given <dg@cowlark.com>
Date: Mon, 25 Nov 2019 20:54:13 +0100
Subject: [PATCH] Clean up the Verilog a bit.

---
 FluxEngine.cydsn/Sequencer/Sequencer.v | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/FluxEngine.cydsn/Sequencer/Sequencer.v b/FluxEngine.cydsn/Sequencer/Sequencer.v
index 795ec38e..f1b2fe9b 100644
--- a/FluxEngine.cydsn/Sequencer/Sequencer.v
+++ b/FluxEngine.cydsn/Sequencer/Sequencer.v
@@ -57,27 +57,18 @@ begin
         countdown <= 0;
     end
     else
-    begin
         case (state)
             STATE_IDLE:
-            begin
                 state <= STATE_LOAD;
-            end
             
             STATE_LOAD:
-            begin
                 if (dataclocked)
-                begin
                     case (opcode)
                         OPCODE_PULSE:
-                        begin
                             state <= STATE_PULSING;
-                        end
                         
                         OPCODE_INDEX:
-                        begin
                             state <= STATE_INDEXING;
-                        end
                         
                         default:
                         begin
@@ -85,38 +76,23 @@ begin
                             state <= STATE_WAITING;
                         end
                     endcase
-                end
-            end
             
             STATE_WAITING:
-            begin
                 if (sampleclocked)
                 begin
                     if (countdown == 0)
-                    begin
                         state <= STATE_LOAD;
-                    end
                     else
-                    begin
                         countdown <= countdown - 1;
-                    end
                 end
-            end
             
             STATE_PULSING:
-            begin
                 state <= STATE_LOAD;
-            end
             
             STATE_INDEXING:
-            begin
                 if (indexed)
-                begin
                     state <= STATE_LOAD;
-                end
-            end
         endcase
-    end
 end
 
 //`#end` -- edit above this line, do not edit this line