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Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a

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little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.
This commit is contained in:
David Given
2019-02-23 19:51:27 +01:00
parent 3752c0681f
commit 34a4c888b5
7 changed files with 65 additions and 36 deletions
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4
FluxEngine.cydsn/main.c
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@@ -257,10 +257,11 @@ static void init_capture_dma(void)
static void cmd_read(struct read_frame* f)
{
SIDE_REG_Write(f->side);
seek_to(current_track);
seek_to(current_track);
/* Do slow setup *before* we go into the real-time bit. */
CAPTURE_RESET_Write(1);
wait_until_writeable(FLUXENGINE_DATA_IN_EP_NUM);
init_capture_dma();
@@ -275,6 +276,7 @@ static void cmd_read(struct read_frame* f)
dma_reading_from_td = -1;
dma_underrun = false;
int count = 0;
CAPTURE_RESET_Write(0);
CyDmaChSetInitialTd(dma_channel, td[dma_writing_to_td]);
CyDmaClearPendingDrq(dma_channel);
CyDmaChEnable(dma_channel, 1);