Merge in jboone's updated sampler branch.

FluxEngine.cydsn/Sampler/Sampler.v

@@ -1,7 +1,6 @@
 
 //`#start header` -- edit after this line, do not edit this line
 `include "cypress.v"
-`include "../SuperCounter/SuperCounter.v"
 
 //`#end` -- edit above this line, do not edit this line
 // Generated on 12/11/2019 at 21:18
@@ -9,7 +8,7 @@
 module Sampler (
 	output [2:0] debug_state,
 	output reg [7:0] opcode,
-	output  req,
+	output  reg       req,
 	input   clock,
 	input   index,
 	input   rdata,
@@ -19,77 +18,62 @@ module Sampler (
 
 //`#start body` -- edit after this line, do not edit this line
 
-localparam STATE_WAITING = 0;
-localparam STATE_OPCODE = 1;
+// NOTE: Reset pulse is used in both clock domains, and must be long enough
+// to be detected in both.
 
-reg [0:0] state;
 reg [5:0] counter;
 
-reg oldsampleclock;
-reg oldindex;
-reg oldrdata;
+reg index_q;
+reg rdata_q;
 
-reg sampleclocked;
-reg indexed;
-reg rdataed;
+reg index_edge;
+reg rdata_edge;
 
-assign req = (state == STATE_OPCODE);
+reg req_toggle;
 
-always @(posedge clock)
+always @(posedge sampleclock)
 begin
     if (reset)
     begin
-        state <= STATE_WAITING;
-        opcode <= 0;
-        sampleclocked <= 0;
-        indexed <= 0;
-        rdataed <= 0;
-        oldsampleclock <= 0;
-        oldindex <= 0;
-        oldrdata <= 0;
+        index_edge <= 0;
+        rdata_edge <= 0;
+        index_q <= 0;
+        rdata_q <= 0;
         counter <= 0;
+        req_toggle <= 0;
     end
     else
     begin
-        /* Remember positive egdes for sampleclock, index and rdata. */
+        /* Both index and rdata are active high -- positive-going edges
+         * indicate the start of an index pulse and read pulse, respectively.
+         */
+         
+        index_edge <= index && !index_q;
+        index_q <= index;
         
-        if (sampleclock && !oldsampleclock)
-            sampleclocked <= 1;
-        oldsampleclock <= sampleclock;
+        rdata_edge <= rdata && !rdata_q;
+        rdata_q <= rdata;
         
-        if (index && !oldindex)
-            indexed <= 1;
-        oldindex <= index;
-        
-        if (rdata && !oldrdata)
-            rdataed <= 1;
-        oldrdata <= rdata;
-        
-        case (state)
-            STATE_WAITING:
-            begin
-                if (sampleclocked)
-                begin
-                    if (rdataed || indexed || (counter == 6'h3f))
-                    begin
-                        opcode <= {rdataed, indexed, counter};
-                        rdataed <= 0;
-                        indexed <= 0;
-                        counter <= 1; /* remember to count this tick */
-                        state <= STATE_OPCODE;
-                    end
-                    else
-                        counter <= counter + 1;
-                        
-                    sampleclocked <= 0;
-                end
-            end
-            
-            STATE_OPCODE: /* opcode sent here */
-            begin
-                state <= STATE_WAITING;
-            end
-        endcase
+        if (rdata_edge || index_edge || (counter == 6'h3f)) begin
+            opcode <= { rdata_edge, index_edge, counter };
+            req_toggle <= ~req_toggle;
+            counter <= 1;   /* remember to count this tick */
+        end else begin
+            counter <= counter + 1;
+        end
+    end
+end
+
+reg req_toggle_q;
+
+always @(posedge clock)
+begin
+    if (reset) begin
+        req_toggle_q <= 0;
+        req <= 0;
+    end else begin
+        req_toggle_q <= req_toggle;
+        req <= (req_toggle != req_toggle_q);
     end
 end