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Attempt to translate the sequencer into Verilog and have it handle long

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intervals properly.
This commit is contained in:
David Given
2019-02-23 00:50:36 +01:00
parent b5c2ddc92e
commit 6a1327e3f6
8 changed files with 76 additions and 19 deletions
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FluxEngine.cydsn/FluxEngine.cyprj
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@@ -3379,6 +3379,6 @@
</ignored_deps>
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
<boot_component v="" />
<current_generation v="19" />
<current_generation v="23" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
</CyXmlSerializer>