Attempt to translate the sequencer into Verilog and have it handle long

intervals properly.
This commit is contained in:
David Given
2019-02-23 00:50:36 +01:00
parent b5c2ddc92e
commit 6a1327e3f6
8 changed files with 76 additions and 19 deletions

View File

@@ -17,6 +17,8 @@ public:
return NULL;
}
Fluxmap& appendInterval(uint32_t ticks);
Fluxmap& appendBytes(const std::vector<uint8_t>& bytes);
Fluxmap& appendBytes(const uint8_t* ptr, size_t len);