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Add a debug UART back on pin 2.0 to get some semblance of debug information off

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the board. Discover a fun edge case where output transfers that were an exact
number of frames weren't being terminated correctly.
This commit is contained in:
David Given
2019-04-06 17:59:23 +02:00
parent 3c2654ea04
commit da8cae61b7
5 changed files with 65 additions and 36 deletions
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34
FluxEngine.cydsn/FluxEngine.cyprj
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@@ -1706,20 +1706,20 @@
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