Rework the output fifo to be a bit more correct about the sync signals, which

in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.

FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex

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 :00000001FF

FluxEngine.cydsn/FIFOout/FIFOout.v

@@ -20,33 +20,34 @@ module FIFOout (
 wire [7:0] po;
 assign d = po;
 
-localparam STATE_WAIT = 1'b0;
-localparam STATE_READ = 1'b1;
+localparam STATE_WAITFORREQ = 0;
+localparam STATE_READFROMFIFO = 1;
+localparam STATE_WAITFORNREQ = 2;
 
-reg state;
-reg oldreq;
+reg [1:0] state;
+wire readfromfifo;
 
-assign ack = (state != STATE_READ);
+assign ack = (state == STATE_WAITFORNREQ);
+assign readfromfifo = (state == STATE_READFROMFIFO);
 
 always @(posedge clk)
 begin
     case (state)
-        STATE_WAIT:
+        /* opcode is not valid; req is low; wait for req to go high. */
+        STATE_WAITFORREQ:
         begin
-            if (!empty)
-            begin
-                if (req && !oldreq)
-                begin
-                    state <= STATE_READ;
-                end
-                oldreq <= req;
-            end
+            if (!empty && req)
+                state <= STATE_READFROMFIFO;
         end
         
-        STATE_READ:
-        begin
-            state <= STATE_WAIT;
-        end
+        /* Fetch a single value from the FIFO. */
+        STATE_READFROMFIFO:
+            state <= STATE_WAITFORNREQ;
+            
+        /* opcode is valid; ack is high. Wait for req to go low. */
+        STATE_WAITFORNREQ:
+            if (!req)
+                state <= STATE_WAITFORREQ;
     endcase
 end
             
@@ -55,11 +56,11 @@ cy_psoc3_dp #(.cy_dpconfig(
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM0: STATE_WAITFORREQ*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM0: idle */
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
-    `CS_CMP_SEL_CFGA, /*CFGRAM1: STATE_LOAD*/
+    `CS_CMP_SEL_CFGA, /*CFGRAM1: read from fifo */
     `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
     `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
     `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
@@ -102,7 +103,7 @@ cy_psoc3_dp #(.cy_dpconfig(
 )) dp(
         /*  input                   */  .reset(1'b0),
         /*  input                   */  .clk(clk),
-        /*  input   [02:00]         */  .cs_addr({2'b0, state}),
+        /*  input   [02:00]         */  .cs_addr({2'b0, readfromfifo}),
         /*  input                   */  .route_si(1'b0),
         /*  input                   */  .route_ci(1'b0),
         /*  input                   */  .f0_load(1'b0),

FluxEngine.cydsn/FluxEngine.cydwr

@@ -851,6 +851,7 @@
       <Data key="4a398466-709f-4228-9500-96178658e13e" value="RDATA" />
       <Data key="5a3407c1-b434-4438-a7b4-b9dfd2280495" value="MOTEA" />
       <Data key="8d318d8b-cf7b-4b6b-b02c-ab1c5c49d0ba" value="SW1" />
+      <Data key="8fc20a4f-e4d1-44b3-a5d4-546e8628d61e" value="LED" />
       <Data key="12e00eac-69b5-4717-85c8-25ef6b224d4c" value="DEBUG_PINS" />
       <Data key="41e2d8ed-5494-4d8c-8ff7-f4f789cece51" value="REDWC" />
       <Data key="264be2d3-9481-494b-8d9c-c1905a45e9cc" value="FDD" />
@@ -3977,6 +3978,11 @@
         <Data key="Port Format" value="2,2" />
       </Group>
     </Group>
+    <Group key="8fc20a4f-e4d1-44b3-a5d4-546e8628d61e">
+      <Group key="0">
+        <Data key="Port Format" value="2,1" />
+      </Group>
+    </Group>
     <Group key="12e00eac-69b5-4717-85c8-25ef6b224d4c">
       <Group key="0">
         <Data key="Port Format" value="2,2" />

FluxEngine.cydsn/FluxEngine.cyprj

@@ -2762,6 +2762,39 @@
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
 <filters />
 </CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainerSerialize" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="LED" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemListSerialize" version="2">
+<dependencies>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="LED_aliases.h" persistent="Generated_Source\PSoC5\LED_aliases.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="HEADER;;;;" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="LED.c" persistent="Generated_Source\PSoC5\LED.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="SOURCE_C;CortexM3;;;" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="LED.h" persistent="Generated_Source\PSoC5\LED.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="HEADER;;;;" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>

FluxEngine.cydsn/Sequencer/Sequencer.v

@@ -40,9 +40,7 @@ always @(posedge clock) olddataclock <= dataclock;
 assign dataclocked = !olddataclock && dataclock;
 
 reg oldsampleclock;
-wire sampleclocked;
-always @(posedge clock) oldsampleclock <= sampleclock;
-assign sampleclocked = !oldsampleclock && sampleclock;
+reg sampleclocked;
 
 reg oldindex;
 wire indexed;
@@ -57,11 +55,18 @@ begin
         countdown <= 0;
     end
     else
+    begin
+        if (!oldsampleclock && sampleclock)
+            sampleclocked <= 1;
+        oldsampleclock <= sampleclock;
+        
         case (state)
             STATE_IDLE:
                 state <= STATE_LOAD;
             
             STATE_LOAD:
+                /* Wait for a posedge on dataclocked, indicating an opcode has
+                 * arrived. */
                 if (dataclocked)
                     case (opcode)
                         OPCODE_PULSE:
@@ -80,10 +85,10 @@ begin
             STATE_WAITING:
                 if (sampleclocked)
                 begin
+                    sampleclocked <= 0;
+                    countdown <= countdown - 1;
                     if (countdown == 0)
                         state <= STATE_LOAD;
-                    else
-                        countdown <= countdown - 1;
                 end
             
             STATE_PULSING:
@@ -92,9 +97,8 @@ begin
             STATE_INDEXING:
                 if (indexed)
                     state <= STATE_LOAD;
-                else
-                    state <= STATE_INDEXING;
         endcase
+    end
 end
 
 //`#end` -- edit above this line, do not edit this line

FluxEngine.cydsn/main.c

@@ -334,7 +334,7 @@ static void cmd_read(struct read_frame* f)
     
     {
         uint8_t i = CyEnterCriticalSection();
-        SAMPLER_FIFO_SET_LEVEL_MID;
+        SAMPLER_FIFO_SET_LEVEL_NORMAL;
         SAMPLER_FIFO_CLEAR;
         SAMPLER_FIFO_SINGLE_BUFFER_UNSET;
         CyExitCriticalSection(i);
@@ -490,7 +490,7 @@ static void cmd_write(struct write_frame* f)
     SIDE_REG_Write(f->side);
     {
         uint8_t i = CyEnterCriticalSection();        
-        REPLAY_FIFO_SET_LEVEL_NORMAL;
+        REPLAY_FIFO_SET_LEVEL_MID;
         REPLAY_FIFO_CLEAR;
         REPLAY_FIFO_SINGLE_BUFFER_UNSET;
         CyExitCriticalSection(i);

protocol.h

@@ -3,7 +3,7 @@
 
 enum 
 {
-    FLUXENGINE_VERSION = 11,
+    FLUXENGINE_VERSION = 12,
 
     FLUXENGINE_VID = 0x1209,
     FLUXENGINE_PID = 0x6e00,