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Abruptly realise that the capture logic was completely missing transitions too

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big to time; so, redesign it. Now the longest transition is 0xfe ticks and a
pulse is inserted if it's too long. Capture is way more robust now and the
resulting pulsetrain is a solid 198ms; and I wrote my first readable disk! (A
PC HD disk. Sadly, writing to the Brother didn't work.)
This commit is contained in:
David Given
2018-10-17 00:26:33 +02:00
parent ed5b9c0b8d
commit e6a424d17a
5 changed files with 16 additions and 35 deletions
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3
FluxEngine.cydsn/main.c
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@@ -242,7 +242,7 @@ static void init_capture_dma(void)
CyDmaTdSetConfiguration(td[i], BUFFER_SIZE, td[nexti],
CY_DMA_TD_INC_DST_ADR | CAPTURE_DMA__TD_TERMOUT_EN);
CyDmaTdSetAddress(td[i], LO16((uint32)CAPTURE_Status_PTR), LO16((uint32)&dma_buffer[i]));
CyDmaTdSetAddress(td[i], LO16((uint32)CAPTURE_COUNTER_STATICCOUNT_LSB_PTR), LO16((uint32)&dma_buffer[i]));
}
}
@@ -546,6 +546,7 @@ int main(void)
INDEX_IRQ_StartEx(&index_irq_cb);
CAPTURE_DMA_FINISHED_IRQ_StartEx(&capture_dma_finished_irq_cb);
REPLAY_DMA_FINISHED_IRQ_StartEx(&replay_dma_finished_irq_cb);
CAPTURE_COUNTER_Start();
UART_Start();
USBFS_Start(0, USBFS_DWR_VDDD_OPERATION);