4 Commits

Author	SHA1	Message	Date
David Given	91d6e9aeb9	Rewrite the sequencer engine with a separate fifo component and a pure verilog ... sequencer --- much easier to understand. We can write disks again!	2019-11-25 20:52:13 +01:00
David Given	1d6f112b53	Remove the old logic-based sequencer.	2019-02-28 21:29:01 +01:00
David Given	462d15369e	Create a pulse generator UDB component --- hopefully cheaper than what we're currently doing.	2019-02-26 23:33:06 +01:00
David Given	6a1327e3f6	Attempt to translate the sequencer into Verilog and have it handle long ... intervals properly.	2019-02-23 00:50:36 +01:00