David Given
df8d45bf66
Rework the output fifo to be a bit more correct about the sync signals, which
...
in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.
2020-02-17 00:13:13 +01:00
David Given
b448ab7917
Finally squeeze everything in to the Verilog sampler. It does seem to work
...
better... the the USB hangup problem persists. Mac disks are still
nigh-unreadable.
2019-12-12 00:12:20 +01:00
David Given
1e012699af
Clean up the Verilog a bit.
2019-11-25 20:54:13 +01:00
David Given
91d6e9aeb9
Rewrite the sequencer engine with a separate fifo component and a pure verilog
...
sequencer --- much easier to understand. We can write disks again!
2019-11-25 20:52:13 +01:00
David Given
1d6f112b53
Remove the old logic-based sequencer.
2019-02-28 21:29:01 +01:00
David Given
462d15369e
Create a pulse generator UDB component --- hopefully cheaper than what we're currently doing.
2019-02-26 23:33:06 +01:00
David Given
34a4c888b5
Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a
...
little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.
2019-02-23 19:51:27 +01:00
David Given
753a4a21ef
Rewrite the sampler Verilog to use much more consistent logic. Still doesn't
...
work for long intervals, though.
2019-02-23 12:42:42 +01:00
David Given
6a1327e3f6
Attempt to translate the sequencer into Verilog and have it handle long
...
intervals properly.
2019-02-23 00:50:36 +01:00
