3 Commits

Author	SHA1	Message	Date
David Given	df8d45bf66	Rework the output fifo to be a bit more correct about the sync signals, which ... in turn allows the sequencer to lose less time --- this gets the effective clock rate down to about 1.01us. However we still seem to lose the last sector on 18-sector disks and there are some disk reads so something is still wrong.	2020-02-17 00:13:13 +01:00
David Given	072a097003	Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've ... run into size limits for the device, and I need to slim down.	2019-12-11 22:51:27 +01:00
David Given	3094c5c919	Add missing files.	2019-11-29 18:49:22 +01:00