David Given df8d45bf66 Rework the output fifo to be a bit more correct about the sync signals, which ...

in turn allows the sequencer to lose less time --- this gets the effective
clock rate down to about 1.01us. However we still seem to lose the last sector
on 18-sector disks and there are some disk reads so something is still wrong.

2020-02-17 00:13:13 +01:00

..

API

Start ripping out the awful UDB-based sampler code, replacing it with a Verilog

2019-12-11 21:13:57 +01:00

FIFOout.cysym

Add missing files.

2019-11-29 18:49:22 +01:00

FIFOout.v

Rework the output fifo to be a bit more correct about the sync signals, which

2020-02-17 00:13:13 +01:00