mirror of
https://github.com/davidgiven/fluxengine.git
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169 lines
6.8 KiB
Verilog
169 lines
6.8 KiB
Verilog
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//`#start header` -- edit after this line, do not edit this line
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`include "cypress.v"
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//`#end` -- edit above this line, do not edit this line
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// Generated on 11/16/2017 at 15:44
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// Component: FIFOout
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module FIFOout (
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input req,
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input clk,
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output [7:0] d,
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output drq,
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output empty,
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output ack
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);
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//`#start body` -- edit after this line, do not edit this line
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/* Reads from the FIFO are done based on the FIFO being not empty. */
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wire [7:0] po;
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assign d = po;
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localparam STATE_WAIT = 1'b0;
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localparam STATE_READ = 1'b1;
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reg state;
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reg oldreq;
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assign ack = (state != STATE_READ);
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always @(posedge clk)
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begin
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case (state)
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STATE_WAIT:
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begin
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if (!empty)
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begin
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if (req && !oldreq)
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begin
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state <= STATE_READ;
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end
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oldreq <= req;
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end
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end
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STATE_READ:
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begin
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state <= STATE_WAIT;
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end
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endcase
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end
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cy_psoc3_dp #(.cy_dpconfig(
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{
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM0: STATE_WAITFORREQ*/
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM1: STATE_LOAD*/
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM2: */
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM3: */
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM4: */
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM5: */
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM6: */
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`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
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`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
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`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
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`CS_CMP_SEL_CFGA, /*CFGRAM7: */
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8'hFF, 8'h00, /*CFG9: */
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8'hFF, 8'hFF, /*CFG11-10: */
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`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
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`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
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`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
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`SC_SI_A_DEFSI, /*CFG13-12: */
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`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
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1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
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`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
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`SC_FB_NOCHN, `SC_CMP1_NOCHN,
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`SC_CMP0_NOCHN, /*CFG15-14: */
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10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
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`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
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`SC_WRK16CAT_DSBL /*CFG17-16: */
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}
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)) dp(
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/* input */ .reset(1'b0),
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/* input */ .clk(clk),
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/* input [02:00] */ .cs_addr({2'b0, state}),
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/* input */ .route_si(1'b0),
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/* input */ .route_ci(1'b0),
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/* input */ .f0_load(1'b0),
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/* input */ .f1_load(1'b0),
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/* input */ .d0_load(1'b0),
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/* input */ .d1_load(1'b0),
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/* output */ .ce0(),
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/* output */ .cl0(),
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/* output */ .z0(),
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/* output */ .ff0(),
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/* output */ .ce1(),
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/* output */ .cl1(),
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/* output */ .z1(),
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/* output */ .ff1(),
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/* output */ .ov_msb(),
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/* output */ .co_msb(),
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/* output */ .cmsb(),
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/* output */ .so(),
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/* output */ .f0_bus_stat(drq), // not full
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/* output */ .f0_blk_stat(empty), // empty
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/* output */ .f1_bus_stat(),
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/* output */ .f1_blk_stat(),
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/* input */ .ci(1'b0), // Carry in from previous stage
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/* output */ .co(),// Carry out to next stage
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/* input */ .sir(1'b0), // Shift in from right side
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/* output */ .sor(), // Shift out to right side
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/* input */ .sil(1'b0), // Shift in from left side
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/* output */ .sol(), // Shift out to left side
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/* input */ .msbi(1'b0), // MSB chain in
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/* output */ .msbo(), // MSB chain out
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/* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage
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/* output [01:00] */ .ceo(), // Compare equal out to next stage
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/* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage
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/* output [01:00] */ .clo(), // Compare less than out to next stage
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/* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage
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/* output [01:00] */ .zo(), // Zero detect out to next stage
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/* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage
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/* output [01:00] */ .fo(), // 0xFF detect out to next stage
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/* input [01:00] */ .capi(2'b0), // Software capture from previous stage
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/* output [01:00] */ .capo(), // Software capture to next stage
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/* input */ .cfbi(1'b0), // CRC Feedback in from previous stage
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/* output */ .cfbo(), // CRC Feedback out to next stage
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/* input [07:00] */ .pi(8'b0), // Parallel data port
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/* output [07:00] */ .po(po) // Parallel data port
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);
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//`#end` -- edit above this line, do not edit this line
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endmodule
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//`#start footer` -- edit after this line, do not edit this line
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//`#end` -- edit above this line, do not edit this line
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