David Given 072a097003 Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've ...

run into size limits for the device, and I need to slim down.

2019-12-11 22:51:27 +01:00

..

CortexM3/ARM_GCC_541/Release

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

FIFOin

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

FIFOout

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

PulseGen

The UDB-based pulse generator is back. The problem was I was trying to write to

2019-02-27 23:34:55 +01:00

Sampler

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

Sequencer

Clean up the Verilog a bit.

2019-11-25 20:54:13 +01:00

SuperCounter

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

TopDesign

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Rewrite the sequencer engine with a separate fifo component and a pure verilog

2019-11-25 20:52:13 +01:00

FluxEngine.cyprj

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

main.c

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00