David Given 34a4c888b5 Rewrite the Verilog *again*, and increase the CPU clock rate --- it's now a ...

little more reliable at reading long intervals off disk, but does seem to be
doing it. I'm going to definitely need some better sampling logic here and
probably a FIFO. But it'll do for now.

2019-02-23 19:51:27 +01:00

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