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salfter/fluxengine
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mirror of https://github.com/davidgiven/fluxengine.git synced 2025-10-31 11:17:01 -07:00
Code Issues Packages Projects Releases Wiki Activity
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3d1ee7a43eb8c7a0f2ecb285d156f57675faa245
fluxengine/FluxEngine.cydsn
History
David Given 2584a25527 Update components and binary.
2021-12-10 19:55:06 +00:00
..
CortexM3/ARM_GCC_541/Release
Update components and binary.
2021-12-10 19:55:06 +00:00
FIFOin
Typo fix. Make sure that both drives get deselected when the motor stops (to
2019-12-12 00:17:59 +01:00
FIFOout
Rework the output fifo to be a bit more correct about the sync signals, which
2020-02-17 00:13:13 +01:00
PulseGen
The UDB-based pulse generator is back. The problem was I was trying to write to
2019-02-27 23:34:55 +01:00
Sampler
Update components and binary.
2021-12-10 19:55:06 +00:00
Sequencer
Update sequencer to not lose one tick from every non-zero interval.
2021-01-18 00:27:00 +01:00
SuperCounter
Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've
2019-12-11 22:51:27 +01:00
TopDesign
Update components and binary.
2021-12-10 19:55:06 +00:00
cyapicallbacks.h
Initial project boilerplate.
2018-09-22 21:44:33 +02:00
FluxEngine.cydwr
Update components and binary.
2021-12-10 19:55:06 +00:00
FluxEngine.cyprj
Update FluxEngine components and rebuild firmware.
2021-05-25 19:11:32 +01:00
main.c
Hard Sectors: Fix index_irq assertion.
2021-05-16 15:41:55 -07:00
patcher.vbs
Finally figure out the secrets of WCID, so we don't need a signed driver to do
2018-09-26 00:37:19 +02:00
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