David Given 6a1327e3f6 Attempt to translate the sequencer into Verilog and have it handle long ...

intervals properly.

2019-02-23 00:50:36 +01:00

..

Sampler

Attempt to translate the sequencer into Verilog and have it handle long

2019-02-23 00:50:36 +01:00

Sequencer

Attempt to translate the sequencer into Verilog and have it handle long

2019-02-23 00:50:36 +01:00

TopDesign

Non-working attempt to replace the playback logic with Verilog.

2019-02-22 21:26:54 +01:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Do a recalibrate when retrying a track read --- it makes things a bit more

2019-02-09 22:55:46 +01:00

FluxEngine.cyprj

Attempt to translate the sequencer into Verilog and have it handle long

2019-02-23 00:50:36 +01:00

main.c

Non-working attempt to replace the playback logic with Verilog.

2019-02-22 21:26:54 +01:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00