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97 lines
2.2 KiB
Verilog
97 lines
2.2 KiB
Verilog
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//`#start header` -- edit after this line, do not edit this line
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`include "cypress.v"
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//`#end` -- edit above this line, do not edit this line
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// Generated on 12/11/2019 at 21:18
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// Component: Sampler
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module Sampler (
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output [2:0] debug_state,
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output reg [7:0] opcode,
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output reg req,
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input clock,
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input index,
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input rdata,
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input reset,
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input sampleclock
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);
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//`#start body` -- edit after this line, do not edit this line
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// NOTE: Reset pulse is used in both clock domains, and must be long enough
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// to be detected in both.
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reg [5:0] counter;
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reg index_edge;
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reg rdata_edge;
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reg req_toggle;
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reg rdata_toggle;
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reg old_rdata_toggle;
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reg index_toggle;
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reg old_index_toggle;
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always @(posedge rdata)
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begin
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rdata_toggle <= ~rdata_toggle;
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end
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always @(posedge index)
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begin
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index_toggle <= ~index_toggle;
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end
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always @(posedge sampleclock)
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begin
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if (reset)
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begin
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old_rdata_toggle <= 0;
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old_index_toggle <= 0;
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index_edge <= 0;
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rdata_edge <= 0;
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counter <= 0;
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req_toggle <= 0;
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end
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else
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begin
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/* If data_toggle or index_toggle have changed state, this means that they've
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* gone high since the last sampleclock. */
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index_edge <= index_toggle != old_index_toggle;
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old_index_toggle <= index_toggle;
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rdata_edge <= rdata_toggle != old_rdata_toggle;
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old_rdata_toggle <= rdata_toggle;
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if (rdata_edge || index_edge || (counter == 6'h3f)) begin
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opcode <= { rdata_edge, index_edge, counter };
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req_toggle <= ~req_toggle;
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counter <= 1; /* remember to count this tick */
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end else begin
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counter <= counter + 1;
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end
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end
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end
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reg req_toggle_q;
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always @(posedge clock)
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begin
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if (reset) begin
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req_toggle_q <= 0;
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req <= 0;
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end else begin
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req_toggle_q <= req_toggle;
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req <= (req_toggle != req_toggle_q);
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end
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end
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//`#end` -- edit above this line, do not edit this line
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endmodule
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//`#start footer` -- edit after this line, do not edit this line
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//`#end` -- edit above this line, do not edit this line
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