David Given da8cae61b7 Add a debug UART back on pin 2.0 to get some semblance of debug information off ...

the board. Discover a fun edge case where output transfers that were an exact
number of frames weren't being terminated correctly.

2019-04-06 17:59:23 +02:00

..

PulseGen

The UDB-based pulse generator is back. The problem was I was trying to write to

2019-02-27 23:34:55 +01:00

TopDesign

Add a debug UART back on pin 2.0 to get some semblance of debug information off

2019-04-06 17:59:23 +02:00

UdbSampler

The sequencer now (I hope, untested) supports waiting for the index hole. It's

2019-03-07 00:10:12 +01:00

UdbSequencer

The sequencer now (I hope, untested) supports waiting for the index hole. It's

2019-03-07 00:10:12 +01:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Add a debug UART back on pin 2.0 to get some semblance of debug information off

2019-04-06 17:59:23 +02:00

FluxEngine.cyprj

Add a debug UART back on pin 2.0 to get some semblance of debug information off

2019-04-06 17:59:23 +02:00

main.c

Add a debug UART back on pin 2.0 to get some semblance of debug information off

2019-04-06 17:59:23 +02:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00