David Given 98ea5e9600 Connect up pins 2.3, 2.4 and 2.5 for debugging with a logic analyser.

2019-07-08 01:08:05 +02:00

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PulseGen

The UDB-based pulse generator is back. The problem was I was trying to write to

2019-02-27 23:34:55 +01:00

TopDesign

Connect up pins 2.3, 2.4 and 2.5 for debugging with a logic analyser.

2019-07-08 01:08:05 +02:00

UdbSampler

The sequencer now (I hope, untested) supports waiting for the index hole. It's

2019-03-07 00:10:12 +01:00

UdbSequencer

The sequencer now (I hope, untested) supports waiting for the index hole. It's

2019-03-07 00:10:12 +01:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Connect up pins 2.3, 2.4 and 2.5 for debugging with a logic analyser.

2019-07-08 01:08:05 +02:00

FluxEngine.cyprj

Connect up pins 2.3, 2.4 and 2.5 for debugging with a logic analyser.

2019-07-08 01:08:05 +02:00

main.c

Better handling of seeks (plus tracing).

2019-05-01 13:06:56 +02:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00