David Given c56459c98c Add back the pulse converter, as a 12MHz sample clock only allows pulses which ...

are 83ns long, which I think is too big. We now sample the index signal at
64MHz which allows pulses down to 16ns.

2021-12-10 17:40:58 +00:00

..

CortexM3/ARM_GCC_541/Release

Update FluxEngine components and rebuild firmware.

2021-05-25 19:11:32 +01:00

FIFOin

Typo fix. Make sure that both drives get deselected when the motor stops (to

2019-12-12 00:17:59 +01:00

FIFOout

Rework the output fifo to be a bit more correct about the sync signals, which

2020-02-17 00:13:13 +01:00

PulseGen

The UDB-based pulse generator is back. The problem was I was trying to write to

2019-02-27 23:34:55 +01:00

Sampler

Update Sampler.v, moving clock domain crossing to FIFO interface.

2020-05-30 21:31:17 -07:00

Sequencer

Update sequencer to not lose one tick from every non-zero interval.

2021-01-18 00:27:00 +01:00

SuperCounter

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

TopDesign

Add back the pulse converter, as a 12MHz sample clock only allows pulses which

2021-12-10 17:40:58 +00:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Update FluxEngine components and rebuild firmware.

2021-05-25 19:11:32 +01:00

FluxEngine.cyprj

Update FluxEngine components and rebuild firmware.

2021-05-25 19:11:32 +01:00

main.c

Hard Sectors: Fix index_irq assertion.

2021-05-16 15:41:55 -07:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00