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salfter/fluxengine
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mirror of https://github.com/davidgiven/fluxengine.git synced 2025-10-31 11:17:01 -07:00
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cdb12f35d44bf72254bc91c73bb80785fa73587b
fluxengine/FluxEngine.cydsn
History
David Given e53b7ecd8b Rebuild firmware.
2021-01-05 01:51:29 +01:00
..
CortexM3/ARM_GCC_541/Release
Rebuild firmware.
2021-01-05 01:51:29 +01:00
FIFOin
Typo fix. Make sure that both drives get deselected when the motor stops (to
2019-12-12 00:17:59 +01:00
FIFOout
Rework the output fifo to be a bit more correct about the sync signals, which
2020-02-17 00:13:13 +01:00
PulseGen
The UDB-based pulse generator is back. The problem was I was trying to write to
2019-02-27 23:34:55 +01:00
Sampler
Update Sampler.v, moving clock domain crossing to FIFO interface.
2020-05-30 21:31:17 -07:00
Sequencer
Fix sequencer bug where intervals of 0 would go horribly wrong.
2021-01-04 22:06:19 +01:00
SuperCounter
Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've
2019-12-11 22:51:27 +01:00
TopDesign
Try multiplexing SIDE1 onto DIR.
2020-09-10 22:07:47 +02:00
cyapicallbacks.h
Initial project boilerplate.
2018-09-22 21:44:33 +02:00
FluxEngine.cydwr
Merge from trunk.
2021-01-05 01:36:54 +01:00
FluxEngine.cyprj
Add the TK43 pin, which goes low when seeking to track 43 or above.
2020-09-10 21:48:30 +02:00
main.c
Try multiplexing SIDE1 onto DIR.
2020-09-10 22:07:47 +02:00
patcher.vbs
Finally figure out the secrets of WCID, so we don't need a signed driver to do
2018-09-26 00:37:19 +02:00
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