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Jared Boone db2ab8841a Update Sampler.v, moving clock domain crossing to FIFO interface. 
Hopefully, I unscrewed the tab/space and line ending mismatches to minimize the diff.
2020-05-30 21:31:17 -07:00
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Sampler.cysym
Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've
2019-12-11 22:51:27 +01:00
Sampler.v
Update Sampler.v, moving clock domain crossing to FIFO interface.
2020-05-30 21:31:17 -07:00