David Given 56a36072f7 Sampler state machine cleanup; more debugging tools for the logic analyser.

2019-07-12 21:09:53 +02:00

..

PulseGen

The UDB-based pulse generator is back. The problem was I was trying to write to

2019-02-27 23:34:55 +01:00

TopDesign

Sampler state machine cleanup; more debugging tools for the logic analyser.

2019-07-12 21:09:53 +02:00

UdbSampler

Sampler state machine cleanup; more debugging tools for the logic analyser.

2019-07-12 21:09:53 +02:00

UdbSequencer

The sequencer now (I hope, untested) supports waiting for the index hole. It's

2019-03-07 00:10:12 +01:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Make sure that CounterClock is actually 12MHz, and not 12-ish MHz. Doesn't

2019-07-10 20:26:17 +02:00

FluxEngine.cyprj

Sampler state machine cleanup; more debugging tools for the logic analyser.

2019-07-12 21:09:53 +02:00

main.c

Sampler state machine cleanup; more debugging tools for the logic analyser.

2019-07-12 21:09:53 +02:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00