Jared Boone db2ab8841a Update Sampler.v, moving clock domain crossing to FIFO interface. ...

Hopefully, I unscrewed the tab/space and line ending mismatches to minimize the diff.

2020-05-30 21:31:17 -07:00

..

CortexM3/ARM_GCC_541/Release

Fix an off-by-one error in the sequencer that should have it generating correct

2020-04-03 22:58:51 +02:00

FIFOin

Typo fix. Make sure that both drives get deselected when the motor stops (to

2019-12-12 00:17:59 +01:00

FIFOout

Rework the output fifo to be a bit more correct about the sync signals, which

2020-02-17 00:13:13 +01:00

PulseGen

The UDB-based pulse generator is back. The problem was I was trying to write to

2019-02-27 23:34:55 +01:00

Sampler

Update Sampler.v, moving clock domain crossing to FIFO interface.

2020-05-30 21:31:17 -07:00

Sequencer

Fix an off-by-one error in the sequencer that should have it generating correct

2020-04-03 22:58:51 +02:00

SuperCounter

Archival (non-functioning) checkin of Verilog-based sampler code. Sadly, we've

2019-12-11 22:51:27 +01:00

TopDesign

Simplify Sampler.

2020-05-20 11:34:29 -07:00

cyapicallbacks.h

Initial project boilerplate.

2018-09-22 21:44:33 +02:00

FluxEngine.cydwr

Remember to bump the protocol number after the bytecode change.

2020-04-03 21:46:51 +02:00

FluxEngine.cyprj

Fix off-by-one sampler error, so now the clock rates are right again.

2020-04-03 22:27:33 +02:00

main.c

Remove some stray tracing (which was causing problems). Fix a potential problem

2020-03-29 23:11:53 +02:00

patcher.vbs

Finally figure out the secrets of WCID, so we don't need a signed driver to do

2018-09-26 00:37:19 +02:00