can't get the 6502 core to build...it seems to be skipped

cputest/cputest.v

@@ -0,0 +1,33 @@
+`default_nettype none
+`include "../verilog-6502/ALU.v"
+`include "../verilog-6502/cpu.v"
+
+// look in pins.pcf for all the pin names on the TinyFPGA BX board
+module cputest (CLK, LED, USBPU);
+    input wire CLK;    // 16MHz clock
+    output wire LED;   // User/boot LED next to power LED
+    output wire USBPU; // USB pull-up resistor
+
+    // drive USB pull-up resistor to '0' to disable USB
+    assign USBPU = 0;
+
+    // The 6502
+    wire [15:0] CPU_AB;
+    reg [7:0] CPU_DI=8'hEA;
+    wire [7:0] CPU_DO;
+    wire CPU_WE;
+    cpu ucpu(
+        .clk(CLK),
+        .reset(1'b1),
+        .AB(CPU_AB),
+        .DI(CPU_DI),
+        .DO(CPU_DO),
+        .WE(CPU_WE),
+        .IRQ(1'b1),
+        .NMI(1'b1),
+        .RDY(1'b1)
+    );
+
+    assign LED=CPU_AB[15];
+
+endmodule