From 5cb0b79110af1082f3a0ff11569de35cc1475e70 Mon Sep 17 00:00:00 2001
From: Scott Alfter <scott@alfter.us>
Date: Thu, 21 Aug 2025 15:32:14 -0700
Subject: [PATCH] add PLL to blinky

---
 blinky/blinky.v     | 27 +++++++++++++++++++++++++--
 blinky_rgb/blinky.v |  2 +-
 cputest/cputest.v   | 18 +++++++++++-------
 3 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/blinky/blinky.v b/blinky/blinky.v
index b37f922..94e7909 100644
--- a/blinky/blinky.v
+++ b/blinky/blinky.v
@@ -1,9 +1,32 @@
 module blinky (input wire CLK, output wire PIN_24);
 
-    localparam N=24;
+    wire CLK_1;
+
+    SB_PLL40_CORE usb_pll_inst (
+        .REFERENCECLK(CLK),
+        .PLLOUTCORE(CLK_1),
+        .RESETB(1),
+        .BYPASS(0)
+    );
+
+    // Fin=16, Fout=1;
+    defparam usb_pll_inst.DIVF = 0; 
+    defparam usb_pll_inst.DIVQ = 4;
+    defparam usb_pll_inst.DIVR = 0; 
+    defparam usb_pll_inst.FILTER_RANGE = 3'b001;
+    defparam usb_pll_inst.FEEDBACK_PATH = "SIMPLE";
+    defparam usb_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+    defparam usb_pll_inst.FDA_FEEDBACK = 4'b0000;
+    defparam usb_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
+    defparam usb_pll_inst.FDA_RELATIVE = 4'b0000;
+    defparam usb_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+    defparam usb_pll_inst.PLLOUT_SELECT = "GENCLK";
+    defparam usb_pll_inst.ENABLE_ICEGATE = 1'b0;
+
+    localparam N=20;
     reg [N:0] counter=0;
 
-    always @(posedge CLK) 
+    always @(posedge CLK_1) 
         counter <= counter+1;
 
     assign PIN_24=counter[N];
diff --git a/blinky_rgb/blinky.v b/blinky_rgb/blinky.v
index 7cd7e39..e79b3b5 100644
--- a/blinky_rgb/blinky.v
+++ b/blinky_rgb/blinky.v
@@ -1,6 +1,6 @@
 // cribbed from https://blog.idorobots.org/entries/upduino-fpga-tutorial.html
 
-module blinky (//input wire clk,
+module blinky (input wire clk,
                output wire led_blue,
                output wire led_green,
                output wire led_red);
diff --git a/cputest/cputest.v b/cputest/cputest.v
index fee6b12..2260a81 100644
--- a/cputest/cputest.v
+++ b/cputest/cputest.v
@@ -1,6 +1,6 @@
 `default_nettype none
-//`include "../verilog-6502/ALU.v"
-//`include "../verilog-6502/cpu.v"
+`include "../verilog-6502/ALU.v"
+`include "../verilog-6502/cpu.v"
 
 // look in pins.pcf for all the pin names on the TinyFPGA BX board
 module cputest (CLK, LED, USBPU);
@@ -13,21 +13,25 @@ module cputest (CLK, LED, USBPU);
 
     // The 6502
     wire [15:0] CPU_AB;
-    reg [7:0] CPU_DI=8'hEA;
+    wire [7:0] CPU_DI=8'hEA;
     wire [7:0] CPU_DO;
-    wire CPU_WE;
+    wire CPU_WE, CPU_IRQ;
+    wire reset;
     cpu ucpu(
         .clk(CLK),
-        .reset(1'b1),
+        .reset(reset),
         .AB(CPU_AB),
         .DI(CPU_DI),
         .DO(CPU_DO),
         .WE(CPU_WE),
-        .IRQ(1'b1),
-        .NMI(1'b1),
+        .IRQ(CPU_IRQ),
+        .NMI(1'b0),
         .RDY(1'b1)
     );
 
+    always @(*)
+        CPU_DI=8'hEA;
+
     assign LED=CPU_AB[15];
 
 endmodule