[submodule "ice-chips-verilog"]
	path = ice-chips-verilog
	url = https://github.com/TimRudy/ice-chips-verilog/
[submodule "open-fpga-verilog-tutorial"]
	path = open-fpga-verilog-tutorial
	url = https://github.com/Obijuan/open-fpga-verilog-tutorial
[submodule "UPduino-v3.0"]
	path = UPduino-v3.0
	url = https://github.com/tinyvision-ai-inc/UPduino-v3.0
[submodule "65C02"]
	path = 65C02
	url = https://github.com/hoglet67/verilog-6502