31 lines
366 B
Verilog
31 lines
366 B
Verilog
`timescale 10ns/1ns
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`include "div3.v"
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module div3_tb;
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reg CLK;
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wire LED;
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initial CLK=0;
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always #1 CLK=~CLK;
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div3 dut (.clk(CLK), .r(1'b1), .q(LED));
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//-- Begin test
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initial begin
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//-- Set the dumpfile
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$dumpfile("div3_tb.vcd");
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//-- Dump everything into the dumpfile
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$dumpvars(0, div3_tb);
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//-- End after 10 time units
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# 100 $finish;
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end
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endmodule
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