33 lines
369 B
Verilog
33 lines
369 B
Verilog
`timescale 10ns/1ns
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module blinky_tb;
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reg CLK;
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wire LED;
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blinky dut (
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.CLK (CLK),
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.PIN_24 (PIN_24)
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);
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initial CLK=0;
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always #1 CLK=~CLK;
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//-- Begin test
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initial begin
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//-- Set the dumpfile
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$dumpfile("blinky_tb.vcd");
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//-- Dump everything into the dumpfile
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$dumpvars(0, blinky_tb);
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//-- End after 10 time units
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# 100000 $finish;
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end
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endmodule
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