48 lines
1.7 KiB
Verilog
48 lines
1.7 KiB
Verilog
`default_nettype none
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/* verilator lint_off RISEFALLDLY */
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/* verilator lint_off DECLFILENAME */
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/* verilator lint_off PINCONNECTEMPTY */
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/* verilator lint_off UNUSEDPARAM */
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/* verilator lint_off ASSIGNDLY */
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`include "../ice-chips-verilog/includes/helper.v"
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`include "../ice-chips-verilog/source-7400/7404.v"
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`include "../ice-chips-verilog/source-7400/7408.v"
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`include "../ice-chips-verilog/source-7400/7432.v"
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`include "../ice-chips-verilog/source-7400/7474.v"
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/* verilator lint_on ASSIGNDLY */
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/* verilator lint_on UNUSEDPARAM */
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/* verilator lint_on PINCONNECTEMPTY */
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/* verilator lint_on DECLFILENAME */
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/* verilator lint_on RISEFALLDLY */
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// cribbed from the baudrate generator here:
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// https://gitlab.alfter.us/salfter/68b50-dual-serial/-/raw/202e1a1a8720a4ca1aa0a76b04521c2a77b40721/68b50-dual-serial.pdf?inline=false
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// (which, in turn, can be found at https://www.onsemi.com/pub/Collateral/AND8001-D.PDF#page=3)
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module div3(clk, r, q);
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input wire clk;
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input wire r;
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output wire q;
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wire [1:0] U3_A;
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wire U3_Y;
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ttl_7408 #(.BLOCKS(1), .WIDTH_IN(2)) U3(.A_2D(U3_A), .Y(U3_Y));
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wire U1A_Q;
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ttl_7474 #(.BLOCKS(1)) U1A(.Preset_bar(1'b1), .Clear_bar(r), .D(U3_Y), .Clk(clk), .Q(U1A_Q), .Q_bar(U3_A[0]));
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wire U1B_Q;
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ttl_7474 #(.BLOCKS(1)) U1B(.Preset_bar(1'b1), .Clear_bar(r), .D(U1A_Q), .Clk(clk), .Q(U1B_Q), .Q_bar(U3_A[1]));
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wire U2C_Y;
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ttl_7404 #(.BLOCKS(1)) U2C(.A(clk), .Y(U2C_Y));
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wire U4A_Q;
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/* verilator lint_off PINCONNECTEMPTY */
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ttl_7474 #(.BLOCKS(1)) U4A(.Preset_bar(1'b1), .Clear_bar(r), .D(U1B_Q), .Clk(U2C_Y), .Q(U4A_Q), .Q_bar());
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/* verilator lint_on PINCONNECTEMPTY */
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ttl_7432 #(.BLOCKS(1), .WIDTH_IN(2)) U8(.A_2D({U1B_Q, U4A_Q}), .Y(q));
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endmodule
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