35 lines
902 B
Verilog
35 lines
902 B
Verilog
// cribbed from https://blog.idorobots.org/entries/upduino-fpga-tutorial.html
|
|
|
|
module blinky (output wire led_blue,
|
|
output wire led_green,
|
|
output wire led_red);
|
|
|
|
wire clk;
|
|
SB_HFOSC inthosc(
|
|
.CLKHFPU(1'b1), // power up
|
|
.CLKHFEN(1'b1), // enable
|
|
.CLKHF(clk)); // drive the clk signal
|
|
|
|
localparam N=23;
|
|
reg [N:0] counter;
|
|
|
|
always @(posedge clk)
|
|
counter <= counter+1;
|
|
|
|
SB_RGBA_DRV rgb (
|
|
.RGBLEDEN (1'b1),
|
|
.RGB0PWM (counter[N]),
|
|
.RGB1PWM (counter[N-1]),
|
|
.RGB2PWM (counter[N-2]),
|
|
.CURREN (1'b1),
|
|
.RGB0 (led_blue),
|
|
.RGB1 (led_green),
|
|
.RGB2 (led_red)
|
|
);
|
|
defparam rgb.CURRENT_MODE = "0b1";
|
|
defparam rgb.RGB0_CURRENT = "0b000001";
|
|
defparam rgb.RGB1_CURRENT = "0b000001";
|
|
defparam rgb.RGB2_CURRENT = "0b000001";
|
|
|
|
endmodule
|