Files
fpga-stuff/blinky/tb_blinky.v

31 lines
586 B
Verilog

`timescale 1ns/10ps //Adjust to suit
module tb_blinky;
wire wire led_blue ;
wire wire led_green ;
blinky uut (
.wire led_blue ( wire led_blue ),
.wire led_green ( wire led_green )
);
parameter PERIOD = 10; //adjust for your timescale
initial begin
$dumpfile("tb_output.vcd");
$dumpvars(2, tb_blinky);
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
initial begin
rst=1'b0;
#(PERIOD*2) rst=~rst;
#PERIOD rst=~rst;
end
`include "user.tb_blinky.v"
endmodule