35 lines
979 B
Verilog
35 lines
979 B
Verilog
module blinky (input wire CLK, output wire PIN_24);
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wire CLK_1;
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SB_PLL40_CORE usb_pll_inst (
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.REFERENCECLK(CLK),
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.PLLOUTCORE(CLK_1),
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.RESETB(1),
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.BYPASS(0)
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);
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// Fin=16, Fout=1;
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defparam usb_pll_inst.DIVF = 0;
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defparam usb_pll_inst.DIVQ = 4;
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defparam usb_pll_inst.DIVR = 0;
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defparam usb_pll_inst.FILTER_RANGE = 3'b001;
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defparam usb_pll_inst.FEEDBACK_PATH = "SIMPLE";
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defparam usb_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
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defparam usb_pll_inst.FDA_FEEDBACK = 4'b0000;
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defparam usb_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
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defparam usb_pll_inst.FDA_RELATIVE = 4'b0000;
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defparam usb_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
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defparam usb_pll_inst.PLLOUT_SELECT = "GENCLK";
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defparam usb_pll_inst.ENABLE_ICEGATE = 1'b0;
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localparam N=20;
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reg [N:0] counter=0;
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always @(posedge CLK_1)
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counter <= counter+1;
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assign PIN_24=counter[N];
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endmodule
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