10 lines
353 B
Plaintext
10 lines
353 B
Plaintext
[submodule "ice-chips-verilog"]
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path = ice-chips-verilog
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url = https://github.com/TimRudy/ice-chips-verilog/
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[submodule "open-fpga-verilog-tutorial"]
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path = open-fpga-verilog-tutorial
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url = https://github.com/Obijuan/open-fpga-verilog-tutorial
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[submodule "UPduino-v3.0"]
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path = UPduino-v3.0
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url = https://github.com/tinyvision-ai-inc/UPduino-v3.0
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