mirror of
https://github.com/keirf/greaseweazle-firmware.git
synced 2025-10-31 11:06:44 -07:00
Support new board V4 Slim
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19
inc/board.h
Normal file
19
inc/board.h
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@@ -0,0 +1,19 @@
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/*
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* board.h
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*
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* Board definitions
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*
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* Written & released by Keir Fraser <keir.xen@gmail.com>
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*
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* This is free and unencumbered software released into the public domain.
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* See the file COPYING for more details, or visit <http://unlicense.org>.
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*/
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struct board_config {
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uint8_t hse_mhz;
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bool_t hse_byp;
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bool_t hs_usb;
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bool_t flippy;
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const struct pin_mapping *user_pins;
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const struct pin_mapping *msel_pins;
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};
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@@ -30,6 +30,7 @@
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#endif
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#include "intrinsics.h"
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#include "board.h"
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#include "time.h"
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#include "timer.h"
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#include "usb.h"
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@@ -23,3 +23,20 @@ void early_fatal(int blinks) __attribute__((noreturn));
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#define AHB_MHZ (SYSCLK_MHZ / 1) /* 144MHz */
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#define APB1_MHZ (SYSCLK_MHZ / 2) /* 72MHz */
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#define APB2_MHZ (SYSCLK_MHZ / 2) /* 72MHz */
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enum {
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F4SM_v4 = 0,
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F4SM_v4_slim,
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};
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/* Core floppy pin assignments vary between F4 submodels (except INDEX, RDATA,
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* and WDATA). All the following assignments are within GPIOB. */
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struct core_floppy_pins {
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uint8_t trk0;
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uint8_t wrprot;
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uint8_t dir;
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uint8_t step;
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uint8_t wgate;
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uint8_t head;
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};
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extern const struct core_floppy_pins *core_floppy_pins;
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@@ -4,6 +4,7 @@
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#define RCC_CFGR_PLLRANGE_GT72MHZ (1u<<31)
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#define RCC_CFGR_PLLMUL_18 ((uint32_t)0x20040000)
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#define RCC_CFGR_USBPSC_3 ((uint32_t)0x08400000)
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#define RCC_CFGR_HSE_PREDIV2 (1u<<17)
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#define RCC_CFGR_APB2PSC_2 (4u<<11)
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#define RCC_CFGR_APB1PSC_2 (4u<< 8)
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@@ -69,12 +69,6 @@ enum {
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F1SM_plus_unbuffered,
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};
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struct board_config {
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bool_t flippy;
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const struct pin_mapping *user_pins;
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const struct pin_mapping *msel_pins;
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};
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/*
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* Local variables:
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* mode: C
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@@ -99,15 +99,6 @@ enum {
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F7SM_v3,
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};
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struct board_config {
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uint8_t hse_mhz;
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bool_t hse_byp;
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bool_t hs_usb;
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bool_t flippy;
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const struct pin_mapping *user_pins;
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const struct pin_mapping *msel_pins;
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};
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void identify_board_config(void);
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/* On reset, SYSCLK=HSI at 16MHz. SYSCLK runs at 2MHz. */
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