mirror of
https://github.com/keirf/greaseweazle-firmware.git
synced 2025-10-31 11:06:44 -07:00
112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* at32/f4.h
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*
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* Core and peripheral registers.
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*
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* Written & released by Keir Fraser <keir.xen@gmail.com>
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*
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* This is free and unencumbered software released into the public domain.
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* See the file COPYING for more details, or visit <http://unlicense.org>.
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*/
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#define CORTEX_M3 1
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/* C pointer types */
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#define BKP volatile struct bkp * const
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#define AFIO volatile struct afio * const
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#define DMA_CHN volatile struct dma_chn * const
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/* C-accessible registers. */
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static STK stk = (struct stk *)STK_BASE;
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static SCB scb = (struct scb *)SCB_BASE;
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static NVIC nvic = (struct nvic *)NVIC_BASE;
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static DBG dbg = (struct dbg *)DBG_BASE;
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static FLASH flash = (struct flash *)FLASH_BASE;
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static PWR pwr = (struct pwr *)PWR_BASE;
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static BKP bkp = (struct bkp *)BKP_BASE;
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static RCC rcc = (struct rcc *)RCC_BASE;
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static IWDG iwdg = (struct iwdg *)IWDG_BASE;
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static GPIO gpioa = (struct gpio *)GPIOA_BASE;
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static GPIO gpiob = (struct gpio *)GPIOB_BASE;
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static GPIO gpioc = (struct gpio *)GPIOC_BASE;
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static GPIO gpiod = (struct gpio *)GPIOD_BASE;
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static GPIO gpioe = (struct gpio *)GPIOE_BASE;
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static GPIO gpiof = (struct gpio *)GPIOF_BASE;
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static GPIO gpiog = (struct gpio *)GPIOG_BASE;
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static AFIO afio = (struct afio *)AFIO_BASE;
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static EXTI exti = (struct exti *)EXTI_BASE;
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static DMA dma1 = (struct dma *)DMA1_BASE;
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static DMA dma2 = (struct dma *)DMA2_BASE;
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static TIM tim1 = (struct tim *)TIM1_BASE;
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static TIM tim2 = (struct tim *)TIM2_BASE;
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static TIM tim3 = (struct tim *)TIM3_BASE;
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static TIM tim4 = (struct tim *)TIM4_BASE;
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static TIM tim5 = (struct tim *)TIM5_BASE;
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static TIM tim6 = (struct tim *)TIM6_BASE;
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static TIM tim7 = (struct tim *)TIM7_BASE;
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static SPI spi1 = (struct spi *)SPI1_BASE;
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static SPI spi2 = (struct spi *)SPI2_BASE;
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static SPI spi3 = (struct spi *)SPI3_BASE;
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static I2C i2c1 = (struct i2c *)I2C1_BASE;
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static I2C i2c2 = (struct i2c *)I2C2_BASE;
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static USART usart1 = (struct usart *)USART1_BASE;
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static USART usart2 = (struct usart *)USART2_BASE;
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static USART usart3 = (struct usart *)USART3_BASE;
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static SER_ID ser_id = (uint32_t *)0x1ffff7e8;
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#define AT32F403 0x02
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#define AT32F413 0x04
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#define AT32F415 0x05
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#define AT32F403A 0x07
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#define AT32F407 0x08
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extern unsigned int at32f4_series;
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void identify_board_config(void);
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/* On reset, SYSCLK=HSI at 8MHz. SYSCLK runs at 1MHz. */
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void early_fatal(int blinks) __attribute__((noreturn));
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#define early_delay_ms(ms) (delay_ticks((ms)*1000))
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#define early_delay_us(us) (delay_ticks((us)*1))
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#define SYSCLK_MHZ 144
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#define AHB_MHZ 144
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#define APB1_MHZ 72
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#define APB2_MHZ 72
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extern unsigned int FLASH_PAGE_SIZE;
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/* No delay required after enabling a peripheral clock, before accessing it. */
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#define peripheral_clock_delay() ((void)0)
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/* No secondary RAM region */
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#define section_ext_ram
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extern unsigned int sram_kb;
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enum {
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F4SM_v4 = 0,
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F4SM_v4_slim,
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};
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/* Core floppy pin assignments vary between F4 submodels (except INDEX, RDATA,
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* and WDATA). All the following assignments are within GPIOB. */
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struct core_floppy_pins {
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uint8_t trk0;
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uint8_t wrprot;
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uint8_t dir;
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uint8_t step;
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uint8_t wgate;
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uint8_t head;
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};
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extern const struct core_floppy_pins *core_floppy_pins;
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/*
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* Local variables:
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* mode: C
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* c-file-style: "Linux"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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