108 lines
3.0 KiB
Plaintext
108 lines
3.0 KiB
Plaintext
# This is the template file for creating symbols with tragesym
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# every line starting with '#' is a comment line.
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# save it as text file with tab separated cells and start tragesym
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[options]
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# wordswap swaps labels if the pin is on the right side an looks like this:
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# "PB1 (CLK)". That's useful for micro controller port labels
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# rotate_labels rotates the pintext of top and bottom pins
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# this is useful for large symbols like FPGAs with more than 100 pins
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# sort_labels will sort the pins by it's labels
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# useful for address ports, busses, ...
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wordswap yes
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rotate_labels no
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sort_labels yes
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generate_pinseq yes
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sym_width 1400
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pinwidthvertical 400
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pinwidthhorizontal 400
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[geda_attr]
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# name will be printed in the top of the symbol
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# if you have a device with slots, you'll have to use slot= and slotdef=
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# use comment= if there are special information you want to add
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version 20060113 1
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name A2BUS
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device A2BUS
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refdes CONN?
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footprint Male_Card-Edge_50_pin__100_mil
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description Apple II expansion bus edge connector
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documentation
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author Scott Alfter
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numslots 0
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dist-license
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use-license
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#slot 1
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#slotdef 1:
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#slotdef 2:
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#slotdef 3:
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#slotdef 4:
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#comment
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#comment
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#comment
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[pins]
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# tabseparated list of pin descriptions
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#
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# pinnr is the physical number of the pin
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# seq is the pinseq= attribute, leave it blank if it doesn't matter
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# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
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# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
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# posit. can be (l,r,t,b) or empty for nets.
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# net specifies the name of the net. Vcc or GND for example.
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# label represents the pinlabel.
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# negation lines can be added with "\_" example: \_enable\_
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# if you want to write a "\" use "\\" as escape sequence
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#
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#pinnr seq type style posit. net label
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1 out dot r \_IOSEL\_
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2 out line r A0
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3 out line r A1
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4 out line r A2
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5 out line r A3
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6 out line r A4
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7 out line r A5
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8 out line r A6
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9 out line r A7
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10 out line r A8
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11 out line r A9
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12 out line r A10
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13 out line r A11
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14 out line r A12
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15 out line r A13
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16 out line r A14
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17 out line r A15
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18 out line r R/\_W\_
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19 out dot r \_SYNC\_
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20 out dot r \_IOSTROBE\_
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21 in line r RDY
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22 in dot r \_DMA\_
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23 out line r INTOUT
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24 out line r DMAOUT
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25 pwr line r +5V
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26 pwr line l GND
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27 in line l DMAIN
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28 in line l INTIN
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29 in dot l \_NMI\_
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30 in dot l \_IRQ\_
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31 in dot l \_RES\_
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32 in dot l \_INH\_
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33 pwr line l -12V
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34 pwr line l -5V
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35 out line l 3.58M
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36 out line l 7M
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37 out line l Q3
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38 clk line l PHI1
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39 out line l UPSYNC
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40 clk line l PHI0
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41 out dot l \_DEVSEL\_
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42 io line l D7
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43 io line l D6
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44 io line l D5
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45 io line l D4
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46 io line l D3
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47 io line l D2
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48 io line l D1
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49 io line l D0
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50 pwr line l +12v
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