From 4084affd5d0490988aacdd105686945cf0e388c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20L=C3=B6her?= Date: Sun, 21 Jul 2024 00:56:43 +0200 Subject: [PATCH] Change clockworks module, because clock domain names are not propagated up the hierarchy anymore (RFC59). --- 02_slower_blinky/soc.py | 2 +- 03_blink_from_rom/soc.py | 2 +- 04_instruction_decoder/soc.py | 2 +- 05_register_bank/soc.py | 2 +- 06_alu/soc.py | 2 +- 07_assembler/soc.py | 2 +- 08_jumps/soc.py | 2 +- 09_branches/soc.py | 2 +- 10_lui_auipc/soc.py | 2 +- 11_modules/soc.py | 2 +- 12_size_optimisation/soc.py | 2 +- 13_subroutines/soc.py | 2 +- 14_subroutines_v2/soc.py | 2 +- 15_load/soc.py | 2 +- 16_store/soc.py | 2 +- 17_memory_map/soc.py | 2 +- 18_mandelbrot/soc.py | 2 +- lib/clockworks.py | 7 ++++++- tests/soc.py | 2 +- 19 files changed, 24 insertions(+), 19 deletions(-) diff --git a/02_slower_blinky/soc.py b/02_slower_blinky/soc.py index 2a44974..0a236ce 100644 --- a/02_slower_blinky/soc.py +++ b/02_slower_blinky/soc.py @@ -19,7 +19,7 @@ class SOC(wiring.Component): count = Signal(5) # Instantiate the clockwork with a divider of 2^21 - cw = Clockworks(slow=21) + cw = Clockworks(m, slow=21) # Add the clockwork to the top module. If this is not done, # the logic will not be instantiated. diff --git a/03_blink_from_rom/soc.py b/03_blink_from_rom/soc.py index f71379b..4614408 100644 --- a/03_blink_from_rom/soc.py +++ b/03_blink_from_rom/soc.py @@ -12,7 +12,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21) + cw = Clockworks(m, slow=21) m.submodules.cw = cw sequence = [ diff --git a/04_instruction_decoder/soc.py b/04_instruction_decoder/soc.py index 2135a6b..c20798a 100644 --- a/04_instruction_decoder/soc.py +++ b/04_instruction_decoder/soc.py @@ -16,7 +16,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21) + cw = Clockworks(m, slow=21) m.submodules.cw = cw # Instruction sequence to be executed diff --git a/05_register_bank/soc.py b/05_register_bank/soc.py index 1f63158..a42e7e1 100644 --- a/05_register_bank/soc.py +++ b/05_register_bank/soc.py @@ -16,7 +16,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21, sim_slow=10) + cw = Clockworks(m, slow=21, sim_slow=10) m.submodules.cw = cw # Instruction sequence to be executed diff --git a/06_alu/soc.py b/06_alu/soc.py index ef7d428..36fc4ca 100644 --- a/06_alu/soc.py +++ b/06_alu/soc.py @@ -16,7 +16,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21, sim_slow=10) + cw = Clockworks(m, slow=21, sim_slow=10) m.submodules.cw = cw # Instruction sequence to be executed diff --git a/07_assembler/soc.py b/07_assembler/soc.py index ec25d4a..72f93f0 100644 --- a/07_assembler/soc.py +++ b/07_assembler/soc.py @@ -38,7 +38,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21, sim_slow=10) + cw = Clockworks(m, slow=21, sim_slow=10) m.submodules.cw = cw # Program counter diff --git a/08_jumps/soc.py b/08_jumps/soc.py index 2d9cc4d..e93e0e3 100644 --- a/08_jumps/soc.py +++ b/08_jumps/soc.py @@ -30,7 +30,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21, sim_slow=10) + cw = Clockworks(m, slow=21, sim_slow=10) m.submodules.cw = cw # Program counter diff --git a/09_branches/soc.py b/09_branches/soc.py index e835d6c..d0852f3 100644 --- a/09_branches/soc.py +++ b/09_branches/soc.py @@ -31,7 +31,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21, sim_slow=10) + cw = Clockworks(m, slow=21, sim_slow=10) m.submodules.cw = cw # Program counter diff --git a/10_lui_auipc/soc.py b/10_lui_auipc/soc.py index 069cb40..ff5a937 100644 --- a/10_lui_auipc/soc.py +++ b/10_lui_auipc/soc.py @@ -28,7 +28,7 @@ class SOC(Elaboratable): m = Module() - cw = Clockworks(slow=21, sim_slow=10) + cw = Clockworks(m, slow=21, sim_slow=10) m.submodules.cw = cw # Program counter diff --git a/11_modules/soc.py b/11_modules/soc.py index 2ddf7af..436de04 100644 --- a/11_modules/soc.py +++ b/11_modules/soc.py @@ -17,7 +17,7 @@ class SOC(Elaboratable): def elaborate(self, platform): m = Module() - cw = Clockworks(slow=19, sim_slow=10) + cw = Clockworks(m, slow=19, sim_slow=10) memory = DomainRenamer("slow")(Memory()) cpu = DomainRenamer("slow")(CPU()) m.submodules.cw = cw diff --git a/12_size_optimisation/soc.py b/12_size_optimisation/soc.py index 2ddf7af..436de04 100644 --- a/12_size_optimisation/soc.py +++ b/12_size_optimisation/soc.py @@ -17,7 +17,7 @@ class SOC(Elaboratable): def elaborate(self, platform): m = Module() - cw = Clockworks(slow=19, sim_slow=10) + cw = Clockworks(m, slow=19, sim_slow=10) memory = DomainRenamer("slow")(Memory()) cpu = DomainRenamer("slow")(CPU()) m.submodules.cw = cw diff --git a/13_subroutines/soc.py b/13_subroutines/soc.py index beba9ea..c984088 100644 --- a/13_subroutines/soc.py +++ b/13_subroutines/soc.py @@ -17,7 +17,7 @@ class SOC(Elaboratable): def elaborate(self, platform): m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Memory()) cpu = DomainRenamer("slow")(CPU()) m.submodules.cw = cw diff --git a/14_subroutines_v2/soc.py b/14_subroutines_v2/soc.py index beba9ea..c984088 100644 --- a/14_subroutines_v2/soc.py +++ b/14_subroutines_v2/soc.py @@ -17,7 +17,7 @@ class SOC(Elaboratable): def elaborate(self, platform): m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Memory()) cpu = DomainRenamer("slow")(CPU()) m.submodules.cw = cw diff --git a/15_load/soc.py b/15_load/soc.py index beba9ea..c984088 100644 --- a/15_load/soc.py +++ b/15_load/soc.py @@ -17,7 +17,7 @@ class SOC(Elaboratable): def elaborate(self, platform): m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Memory()) cpu = DomainRenamer("slow")(CPU()) m.submodules.cw = cw diff --git a/16_store/soc.py b/16_store/soc.py index d753bd6..1e2c318 100644 --- a/16_store/soc.py +++ b/16_store/soc.py @@ -17,7 +17,7 @@ class SOC(Elaboratable): def elaborate(self, platform): m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Memory()) cpu = DomainRenamer("slow")(CPU()) m.submodules.cw = cw diff --git a/17_memory_map/soc.py b/17_memory_map/soc.py index b2a7e1d..3c7e34c 100644 --- a/17_memory_map/soc.py +++ b/17_memory_map/soc.py @@ -22,7 +22,7 @@ class SOC(Elaboratable): print("clock frequency = {}".format(clk_frequency)) m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Mem()) cpu = DomainRenamer("slow")(CPU()) uart_tx = DomainRenamer("slow")( diff --git a/18_mandelbrot/soc.py b/18_mandelbrot/soc.py index 9b18705..15a0d4b 100644 --- a/18_mandelbrot/soc.py +++ b/18_mandelbrot/soc.py @@ -22,7 +22,7 @@ class SOC(Elaboratable): print("clock frequency = {}".format(clk_frequency)) m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Mem()) cpu = DomainRenamer("slow")(CPU()) uart_tx = DomainRenamer("slow")( diff --git a/lib/clockworks.py b/lib/clockworks.py index 21a275f..7a85b1b 100644 --- a/lib/clockworks.py +++ b/lib/clockworks.py @@ -4,11 +4,16 @@ from amaranth.lib.wiring import In, Out # This module handles clock division and provides a new 'slow' clock domain +clockworks_domain_name = "slow" + class Clockworks(wiring.Component): o_slow: Out(1) - def __init__(self, slow=0, sim_slow=None): + def __init__(self, module, slow=0, sim_slow=None): + + # Since amaranth 0.6 clock domains do not propagate upwards (RFC59) + module.domains += ClockDomain(clockworks_domain_name) # Since the module provides a new clock domain, which is accessible # via the top level module, we don't need to explicitly provide the diff --git a/tests/soc.py b/tests/soc.py index e93d584..8a9453f 100644 --- a/tests/soc.py +++ b/tests/soc.py @@ -21,7 +21,7 @@ class SOC(Elaboratable): simulation = platform is None m = Module() - cw = Clockworks() + cw = Clockworks(m) memory = DomainRenamer("slow")(Mem(simulation=simulation)) cpu = DomainRenamer("slow")(CPU()) uart_tx = DomainRenamer("slow")(