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Remove restriction to 12 MHz clock. Try to use default clock frequency of board.

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This commit is contained in:
Bastian Löher
2023-04-06 04:32:01 +02:00
parent 0e1ae51b2b
commit 764d01d2ee
2 changed files with 8 additions and 2 deletions
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5
17_memory_map/soc.py
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@@ -18,12 +18,15 @@ class SOC(Elaboratable):
def elaborate(self, platform): def elaborate(self, platform):
clk_frequency = int(platform.default_clk_constraint.frequency)
print("clock frequency = {}".format(clk_frequency))
m = Module() m = Module()
cw = Clockworks() cw = Clockworks()
memory = DomainRenamer("slow")(Mem()) memory = DomainRenamer("slow")(Mem())
cpu = DomainRenamer("slow")(CPU()) cpu = DomainRenamer("slow")(CPU())
uart_tx = DomainRenamer("slow")( uart_tx = DomainRenamer("slow")(
UartTx(freq_hz=12*1000000, baud_rate=1000000)) UartTx(freq_hz=clk_frequency, baud_rate=1000000))
m.submodules.cw = cw m.submodules.cw = cw
m.submodules.cpu = cpu m.submodules.cpu = cpu

5
18_mandelbrot/soc.py
View File

@@ -18,12 +18,15 @@ class SOC(Elaboratable):
def elaborate(self, platform): def elaborate(self, platform):
clk_frequency = int(platform.default_clk_constraint.frequency)
print("clock frequency = {}".format(clk_frequency))
m = Module() m = Module()
cw = Clockworks() cw = Clockworks()
memory = DomainRenamer("slow")(Mem()) memory = DomainRenamer("slow")(Mem())
cpu = DomainRenamer("slow")(CPU()) cpu = DomainRenamer("slow")(CPU())
uart_tx = DomainRenamer("slow")( uart_tx = DomainRenamer("slow")(
UartTx(freq_hz=12*1000000, baud_rate=1000000)) UartTx(freq_hz=clk_frequency, baud_rate=1000000))
m.submodules.cw = cw m.submodules.cw = cw
m.submodules.cpu = cpu m.submodules.cpu = cpu