44 lines
1.3 KiB
Python
44 lines
1.3 KiB
Python
from amaranth import *
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from amaranth.sim import *
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from soc import SOC
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soc = SOC()
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sim = Simulator(soc)
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prev_clk = 0
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def proc():
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while True:
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global prev_clk
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clk = yield soc.slow_clk
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if prev_clk == 0 and prev_clk != clk:
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print("pc={}".format((yield soc.pc)))
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print("instr={:#032b}".format((yield soc.instr)))
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print("LEDS = {:05b}".format((yield soc.leds)))
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if (yield soc.isALUreg):
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print("ALUreg rd={} rs1={} rs2={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.rs2Id),
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(yield soc.funct3)))
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if (yield soc.isALUimm):
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print("ALUimm rd={} rs1={} imm={} funct3={}".format(
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(yield soc.rdId), (yield soc.rs1Id), (yield soc.Iimm),
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(yield soc.funct3)))
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if (yield soc.isLoad):
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print("LOAD")
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if (yield soc.isStore):
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print("STORE")
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if (yield soc.isSystem):
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print("SYSTEM")
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break
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yield
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prev_clk = clk
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('bench.vcd', 'bench.gtkw', traces=soc.ports):
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# Let's run for a quite long time
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sim.run_until(2, )
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