136 lines
4.5 KiB
Python
136 lines
4.5 KiB
Python
import sys
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from amaranth import *
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from clockworks import Clockworks
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class SOC(Elaboratable):
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def __init__(self):
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self.leds = Signal(5)
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# Signals in this list can easily be plotted as vcd traces
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self.ports = []
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def elaborate(self, platform):
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m = Module()
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cw = Clockworks(slow=21)
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m.submodules.cw = cw
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# Instruction sequence to be executed
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sequence = [
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# 24 16 8 0
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# .......|.......|.......|.......|
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#R rs2 rs1 f3 rd op
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#I imm rs1 f3 rd op
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#S imm rs2 rs1 f3 imm op
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# ......|....|....|..|....|......|
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0b00000000000000000000000000110011, # R add x0, x0, x0
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0b00000000000000000000000010110011, # R add x1, x0, x0
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0b00000000000100001000000010010011, # I addi x1, x1, 1
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0b00000000000100001000000010010011, # I addi x1, x1, 1
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0b00000000000100001000000010010011, # I addi x1, x1, 1
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0b00000000000100001000000010010011, # I addi x1, x1, 1
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0b00000000000000001010000100000011, # I lw x2, 0(x1)
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0b00000000000100010010000000100011, # S sw x2, 0(x1)
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0b00000000000100000000000001110011 # S ebreak
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]
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# Program counter
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pc = Signal(32)
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# Current instruction
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instr = Signal(32, reset=0b0110011)
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# Instruction memory initialised with above 'sequence'
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mem = Array([Signal(32, reset=x) for x in sequence])
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# Register bank
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regs = Array([Signal(32) for x in range(32)])
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rs1 = Signal(32)
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rs2 = Signal(32)
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writeBackData = C(0)
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writeBackEn = C(0)
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# Opcode decoder
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isALUreg = (instr[0:7] == 0b0110011)
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isALUimm = (instr[0:7] == 0b0010011)
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isBranch = (instr[0:7] == 0b1100011)
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isJALR = (instr[0:7] == 0b1100111)
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isJAL = (instr[0:7] == 0b1101111)
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isAUIPC = (instr[0:7] == 0b0010111)
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isLUI = (instr[0:7] == 0b0110111)
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isLoad = (instr[0:7] == 0b0000011)
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isStore = (instr[0:7] == 0b0100011)
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isSystem = (instr[0:7] == 0b1110011)
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# Immediate format decoder
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Uimm = (Cat(Repl(0, 12), instr[12:32]))
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Iimm = (Cat(instr[20:31], Repl(instr[31], 21)))
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Simm = (Cat(instr[7:12], Cat(instr[25:31], Repl(instr[31], 21)))),
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Bimm = (Cat(0, Cat(instr[8:12], Cat(instr[25:31], Cat(
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instr[7], Repl(instr[31], 20))))))
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Jimm = (Cat(0, Cat(instr[21:31], Cat(instr[20], Cat(
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instr[12:20], Repl(instr[31], 12))))))
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# Register addresses decoder
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rs1Id = (instr[15:20])
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rs2Id = (instr[20:25])
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rdId = ( instr[7:12])
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# Function code decdore
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funct3 = (instr[12:15])
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funct7 = (instr[25:32])
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# Data write back
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with m.If(writeBackEn & (rdId != 0)):
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m.d.slow += regs[rdId].eq(writeBackData)
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# Main state machine
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with m.FSM(reset="FETCH_INSTR") as fsm:
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# Assign important signals to LEDS
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m.d.comb += self.leds.eq(Mux(isSystem, 31, (1 << fsm.state)))
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with m.State("FETCH_INSTR"):
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m.d.slow += instr.eq(mem[pc])
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m.next = "FETCH_REGS"
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with m.State("FETCH_REGS"):
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m.d.slow += [
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rs1.eq(regs[rs1Id]),
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rs2.eq(regs[rs2Id])
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]
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m.next = "EXECUTE"
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with m.State("EXECUTE"):
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m.d.slow += pc.eq(pc + 1)
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m.next = "FETCH_INSTR"
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# Export signals for simulation
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def export(signal, name):
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if type(signal) is not Signal:
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newsig = Signal(signal.shape(), name = name)
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m.d.comb += newsig.eq(signal)
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else:
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newsig = signal
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self.ports.append(newsig)
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setattr(self, name, newsig)
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if platform is None:
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export(ClockSignal("slow"), "slow_clk")
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export(pc, "pc")
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export(instr, "instr")
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export(isALUreg, "isALUreg")
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export(isALUimm, "isALUimm")
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export(isLoad, "isLoad")
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export(isStore, "isStore")
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export(isSystem, "isSystem")
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export(rdId, "rdId")
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export(rs1Id, "rs1Id")
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export(rs2Id, "rs2Id")
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export(Iimm, "Iimm")
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export(funct3, "funct3")
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return m
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