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Fixes.

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Bruno Levy
2022-08-27 22:27:55 +02:00
parent 3f60b52e9c
commit 040cfd7668
2 changed files with 9 additions and 6 deletions
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10
FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/PIPELINE.md
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@@ -512,7 +512,7 @@ has all the stages, but drive it with a state machine that executes one stage at
instead of running them concurrently. Then we will see what needs to be modified when
all the stages run concurrently.
Following all good books in processor design (Patterson, Harris...) we will start
Following all good books in processor design (Patterson & Hennessy, Harris & Harris) we will start
with a super classical design with 5 stages:
| acronym | long name | description |
@@ -612,7 +612,7 @@ Let us summarize the rules:
else is done to the result;
Or put differently: in state `B`, on the left of `<=` there can be only a `BC_`-prefixed
register. On the right of `<=` or `=` there can be only a `BC_`-prefixed register, a `B_`-prefixed
register. On the right of `<=` or `=` there can be only a `AB_`-prefixed register, a `B_`-prefixed
wire or some combinations of these...
However, there are two **exceptions to the rules** (else it would be too simple !):
@@ -1326,7 +1326,7 @@ pipeline. Can we blow less bubbles in there ?
## Step 5: reading and writing the register file in the same cycle
If you read the good books on processor design (Patterson, Harris and Harris), they say that
If you read the good books on processor design (Patterson and Hennessy, Harris and Harris), they say that
the data written to the register file by `W` can be read by `D` *in the same cycle*, so why
do we stall until the instruction leaves `W` ?
@@ -1378,7 +1378,7 @@ The source is in [pipeline5.v](pipeline5.v).
Let us see now how to "do it right", with a combinatorial access in the register file,
so that we really can write the register file and read it in the same cycle, as described
in the good books (Patterson, Harris & Harris):
in the good books (Patterson & Hennessy, Harris & Harris):
```verilog
reg [31:0] RegisterBank [0:31];
@@ -1531,7 +1531,7 @@ the ULX3S:
a combinatorial register file (emulated or real) where a written
value can be read in the same cycle (hence pipeline control logic
is simpler)
- ... and finally it drops again when we add register forwaring logic.
- ... and finally it drops again when we add register forwarding logic.
But we made no effort optimizing Fmax, our goal up to now was mainly to
reduce CPI. Let us see what we can do now.

5
README.md
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@@ -31,11 +31,14 @@ it from this repository when selected as the SoC's processor).
From Blinky to RISC-V
---------------------
In [this tutorial](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md),
In [Episode I](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/README.md),
you will learn to build your own RISC-V processor, step by step,
starting from the simplest design (that blinks a LED), to a fully
functional RISC-V core that can compute and display graphics.
In [Episode II](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/PIPELINE.md),
you will learn how to design a pipelined processor.
Basic: more basic things I wrote during May 2020 - June 2020
------------------------------------------------------------
Files are [here](https://github.com/BrunoLevy/learn-fpga/tree/master/Basic).