Fixed typo: reg [31:0] aluOut = aluReg ---> wire [31:0] aluOut = aluReg

2021-03-31 22:23:05 +02:00
parent 972e3f3c4e
commit 0654074f2d
5 changed files with 7 additions and 7 deletions
--- a/Basic/FOMU_VGA/vga.v
+++ b/Basic/FOMU_VGA/vga.v
@@ -27,9 +27,9 @@ module vga (

   wire   pixel_clk;

-//`define VGA_MODE_640x480
+`define VGA_MODE_640x480
 //`define VGA_MODE_1024x768
-`define VGA_MODE_1280x1024
+//`define VGA_MODE_1280x1024

 `ifdef VGA_MODE_640x480
   // PLL: converts system clock (48 MHz) to pixel clock (25.125 MHz for 640x480)