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Added latched output buffer to the 4 pins, improves stability and image

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quality a lot ! (and now higher res sort of works)
This commit is contained in:
Bruno Levy
2021-04-24 08:46:04 +02:00
parent 3ae30f3ad5
commit 78bbcc70d0
1 changed files with 24 additions and 17 deletions
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41
Basic/FOMU/FOMU_VGA/vga.v
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@@ -27,6 +27,7 @@ module vga (
wire pixel_clk;
// Choose your video mode here:
`define VGA_MODE_640x480
//`define VGA_MODE_1024x768
//`define VGA_MODE_1280x1024
@@ -112,6 +113,7 @@ module vga (
parameter VGA_v_back_porch = 38;
`endif
// Generic VGA signal generator, based on video mode constants
parameter VGA_line_width = VGA_width + VGA_h_front_porch + VGA_h_sync_width + VGA_h_back_porch;
parameter VGA_lines = VGA_height + VGA_v_front_porch + VGA_v_sync_width + VGA_v_back_porch;
@@ -137,14 +139,16 @@ module vga (
VGA_vSync <= (VGA_Y>=VGA_height+VGA_v_front_porch) && (VGA_Y<VGA_height+VGA_v_front_porch+VGA_v_sync_width);
end
wire [1:0] out_color;
// The two-bits pixel color (because we have only two output wires for color on the FOMU)
reg [1:0] out_color;
// Demo 1
// ****************** Demo 1: hypnotic concentric cycles ****************************************************
wire signed [11:0] dx = $signed(VGA_X) - VGA_width/2;
wire signed [11:0] dy = $signed(VGA_Y) - VGA_height/2;
wire signed [23:0] R2 = dx*dx + dy*dy - $signed(VGA_frame << 6);
wire [3:0] color_4 = R2[14:11];
// ordered dithering to simulate 16 colors from the generated 4 colors
reg [1:0] threshold;
always @(*) begin
case({VGA_X[0],VGA_Y[0]})
@@ -156,26 +160,29 @@ module vga (
end
wire [1:0] demo_1 = (color_4[1:0] <= threshold) | (&color_4[3:2]) ? color_4[3:2] : color_4[3:2]+1;
assign out_color = !VGA_DrawArea ? 2'b00 : demo_1 ;
// Demo 2
/*
// ******************* Demo 2: "Alian Art" XOR/Modulo pattern (two layers) **********************************
wire b1 = ((((VGA_Y >> 1) - VGA_frame) ^ VGA_X >> 1)%10'd9 == 1);
wire b2 = (((VGA_Y - (VGA_frame >> 1))^ VGA_X)%10'd13 == 1);
wire [1:0] demo_2 = {b1,b2};
assign out_color = !VGA_DrawArea ? 2'b00 :
VGA_frame[8] ? demo_1 : demo_2 ;
*/
// **********************************************************************************************************
always @(posedge pixel_clk) begin
// out_color <= demo_1;
out_color <= VGA_frame[8] ? demo_1 : demo_2 ;
end
assign user_1 = VGA_hSync;
assign user_2 = VGA_vSync;
assign user_3 = out_color[0];
assign user_4 = out_color[1];
// LED driver
// Four latched IO pins: fixes the tiny differences of signal propagation
// time that would result in a blurry / glitchy image.
SB_IO #(
.PIN_TYPE(5'b0101_00) // 0101: latched output 00: no input
) user_IO[3:0] ( // Yes, in Verilog you can declare 4 pins in 1 decl
.PACKAGE_PIN({user_1,user_2,user_3,user_4}),
.D_OUT_0({VGA_hSync, VGA_vSync, VGA_DrawArea ? out_color : 2'b00}),
.OUTPUT_CLK({4{pixel_clk}})
);
// LED driver: generate a blinky to show whether the design is active
// Note: the LED driver is more intelligent than I wish, it changes color
// at the same frequency whatever the bit of frame I'm using, I need to
// understand what's going on here (supposed to be a PWM, maybe I should