More info about VGA
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@@ -98,15 +98,27 @@ and three wires for the USB that should be set to 0 if not used.
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Next section of the file is a VGA generator. I have implemented three different
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modes (640x480, 1024x768, 1280x1024). Each mode defines some parameters
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(width, height of course, plus some timings for horizontal and
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vertical sync, plus the frequency of the pixel clock). To generate the
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pixel clock, you will need to transform the 48 MHz clock of the FOMU
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modes (640x480, 1024x768, 1280x1024). Each mode defines some parameters:
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- resolution in pixels: width, height
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- horizontal sync: h_front_porch, hsync_width, h_back_porch
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- vertical sync: v_front_porch, vsync_width, v_back_porch
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- pixel clock
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After each line of pixels, there is a blanking period (horizontal
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front porch), then a pulse of the hsync signal, then another blanking
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period (horizontal back proch), and same thing after each frame (
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vertical front porch, pulse of vsync, then vertical back porch). The
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widths of the front/back porch and sync pulses are all given in 'pixels'.
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_some authors start each pixel row with the back porch, then pixel
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data, then front porch and sync, which I find less natural_.
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The timings are standard, and can be found for instance
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[here](http://martin.hinner.info/vga/timing.html). To generate the pixel clock,
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you will need to transform the 48 MHz clock of the FOMU
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into another frequency (for instance, 25 MHz for 640x480). This is done
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by a special FPGA primitive (`SB_PLL40_CORE` for the ICE40UP5k used by
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the FOMU). To find the correct parameters, you can use the `icepll`
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utility. For instance, for 640x480, you need a 25 MHz pixel clock, then
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`icepll -i 48 -o 25` will give you the parameters to configure the
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utility. For instance, for 640x480, you need a 25.175 MHz pixel clock, then
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`icepll -i 48 -o 25.175` will give you the parameters to configure the
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`SB_PLL40_CORE`.
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Then there is the generic part of the VGA generator, that will scan all `VGA_X` and
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