44 lines
605 B
Verilog
44 lines
605 B
Verilog
/**
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* Step 1: simulation of a Blinker
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* Usage:
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* iverilog step1.v
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* vvp a.out
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* to exit: <ctrl><c> then finish
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*/
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`default_nettype none
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module Blink (
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input clock,
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output led
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);
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reg count;
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initial begin
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count = 0;
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end
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always @(posedge clock) begin
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count <= ~count;
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end
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assign led = count;
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endmodule
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module bench();
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reg clock;
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wire led;
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Blink uut(
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.clock(clock),
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.led(led)
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);
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initial begin
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clock = 0;
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forever begin
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#1 clock = ~clock;
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$display("LED = %b",led);
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end
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end
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endmodule
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