170 lines
4.5 KiB
Verilog
170 lines
4.5 KiB
Verilog
/**
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* Step 5: Creating a RISC-V processor
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* The register bank and the state machine
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* Usage:
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* iverilog step1.v
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* vvp a.out
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* to exit: <ctrl><c> then finish
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*/
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`default_nettype none
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module RiscV (
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input clock,
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output [4:0] leds
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);
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assign leds = 0; // we will use the LEDs later
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reg [31:0] ROM [0:255];
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reg [31:0] PC; // program counter
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reg [31:0] instr; // current instruction
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initial begin
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PC = 0;
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// add x0, x0, x0
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// rs2 rs1 add rd ALUREG
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instr = 32'b0000000_00000_00000_000_00000_0110011;
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// add x1, x0, x0
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// rs2 rs1 add rd ALUREG
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ROM[0] = 32'b0000000_00000_00000_000_00001_0110011;
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// addi x1, x1, 1
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// imm rs1 add rd ALUIMM
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ROM[1] = 32'b000000000001_00001_000_00001_0010011;
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// addi x1, x1, 1
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// imm rs1 add rd ALUIMM
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ROM[2] = 32'b000000000001_00001_000_00001_0010011;
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// addi x1, x1, 1
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// imm rs1 add rd ALUIMM
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ROM[3] = 32'b000000000001_00001_000_00001_0010011;
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// addi x1, x1, 1
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// imm rs1 add rd ALUIMM
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ROM[4] = 32'b000000000001_00001_000_00001_0010011;
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ROM[5] = 0;
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end
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// See the table P. 105 in RISC-V manual
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// The 10 RISC-V instructions
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wire isALUreg = (instr[6:0] == 7'b0110011); // rd <- rs1 OP rs2
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wire isALUimm = (instr[6:0] == 7'b0010011); // rd <- rs1 OP Iimm
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wire isBranch = (instr[6:0] == 7'b1100011); // if(rs1 OP rs2) PC<-PC+Bimm
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wire isJALR = (instr[6:0] == 7'b1100111); // rd <- PC+4; PC<-rs1+Iimm
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wire isJAL = (instr[6:0] == 7'b1101111); // rd <- PC+4; PC<-PC+Jimm
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wire isAUIPC = (instr[6:0] == 7'b0010111); // rd <- PC + Uimm
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wire isLUI = (instr[6:0] == 7'b0110111); // rd <- Uimm
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wire isLoad = (instr[6:0] == 7'b0000011); // rd <- mem[rs1+Iimm]
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wire isStore = (instr[6:0] == 7'b0100011); // mem[rs1+Simm] <- rs2
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wire isSYSTEM = (instr[6:0] == 7'b1110011); // special
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// The 5 immediate formats
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wire [31:0] Uimm={ instr[31], instr[30:12], {12{1'b0}}};
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wire [31:0] Iimm={{21{instr[31]}}, instr[30:20]};
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wire [31:0] Simm={{21{instr[31]}}, instr[30:25],instr[11:7]};
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wire [31:0] Bimm={{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
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wire [31:0] Jimm={{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
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// Source and destination registers
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wire [4:0] rs1Id = instr[19:15];
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wire [4:0] rs2Id = instr[24:20];
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wire [4:0] rdId = instr[11:7];
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// function codes
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wire [2:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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// The registers bank
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reg [31:0] RegisterBank [0:31];
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reg [31:0] rs1;
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reg [31:0] rs2;
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wire [31:0] writeBackData;
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wire writeBackEn;
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assign writeBackData = 0; // for now
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assign writeBackEn = 0; // for now
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integer i;
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initial begin
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for(i=0; i<32; ++i) begin
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RegisterBank[i] = 0;
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end
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end
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// The state machine
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localparam FETCH_INSTR = 0;
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localparam FETCH_REGS = 1;
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localparam EXECUTE = 2;
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reg [1:0] state;
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initial begin
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state = FETCH_INSTR;
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end
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always @(posedge clock) begin
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if(writeBackEn && rdId != 0) begin
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RegisterBank[rdId] <= writeBackData;
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end
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case(state)
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FETCH_INSTR: begin
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instr <= ROM[PC];
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state <= FETCH_REGS;
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end
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FETCH_REGS: begin
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rs1 <= RegisterBank[rs1Id];
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rs2 <= RegisterBank[rs2Id];
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state <= EXECUTE;
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end
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EXECUTE: begin
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case (1'b1)
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isALUreg: $display(
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"ALUreg rd=%d rs1=%d rs2=%d funct3=%b",
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rdId, rs1Id, rs2Id, funct3
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);
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isALUimm: $display(
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"ALUimm rd=%d rs1=%d imm=%0d funct3=%b",
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rdId, rs1Id, Iimm, funct3
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);
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isBranch: $display("BRANCH");
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isJAL: $display("JAL");
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isJALR: $display("JALR");
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isAUIPC: $display("AUIPC");
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isLUI: $display("LUI");
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isLoad: $display("LOAD");
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isStore: $display("STORE");
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isSYSTEM: $display("SYSTEM");
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endcase
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if(instr == 0) begin
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$finish();
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end
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PC <= PC + 1;
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state <= FETCH_INSTR;
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end
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endcase
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end
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endmodule
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module bench();
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reg clock;
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wire [4:0] leds;
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RiscV uut(
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.clock(clock),
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.leds(leds)
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);
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initial begin
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clock = 0;
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forever begin
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#1 clock = ~clock;
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// $display("LEDS=%b",leds); // we will use the LEDs later
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end
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end
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endmodule
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